EPC2L120N vs EPC2L20N Comparison
Detailed side-by-side comparison of EPC2L120N by Intel and EPC2L20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2L120N | EPC2L20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.85 | $17.20 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | β |
| Manufacturer | Intel (formerly Altera) | β |
| Family | EPC2 (Enhanced Configuration Device) | β |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | β |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | β |
| 5V Tolerance | Yes (5V-tolerant I/O) | β |
| Configuration Clock (FPP) | Up to 66 MHz | β |
| Configuration Clock (PS) | Up to 33 MHz | β |
| Internal Oscillator | 8 MHz with programmable divider | β |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | β |
| Programming Cycles | 100,000 erase/program cycles | β |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | β |
| Package | 84-pin PLCC (J-Lead) | β |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | β |
| Operating Temperature | [DATA_NEEDED: industrial temp range] | 0C to +70C (commercial) |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| RoHS Status | unknown | Compliant |
| Function | β | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Memory Size | β | 1.6 Mbit |
| Programmable Type | β | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | β | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| Package / Case | β | 20-LCC (J-Lead), PLCC-20 |
| Packaging | β | Tube |
| Configuration Interface | β | Serial (Altera FPP / PS configuration scheme) |
| Cascade Support | β | Yes (multi-PROM chain via CE control) |
| Programming Method | β | In-system via 4-wire ISP / JTAG-style |
| Mounting Type | β | Surface Mount (J-Lead PLCC) |
| Pin Count | β | 20 |
| Lead Finish | β | Matte Tin (Pb-free) |
| MSL Level | β | 3 (168 hours) |