EPC8QI100N vs EPC8QC100DM 比較
詳細な並列比較: EPC8QI100N メーカー: Altera および EPC8QC100DM メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC8QI100N | EPC8QC100DM |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | EEPROM | EEPROM |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $16.90 | $17.10 |
| Manufacturer | Altera (Intel) | — |
| Part Family | EPC8 (Enhanced Configuration) | — |
| Device Type | Configuration PROM for SRAM-based FPGAs | — |
| メモリサイズ | 8 Mbit (8,388,608 bits) | 8 Mb (1 MB) |
| Programmable Type | In System Programmable (Flash) | — |
| Configuration Interface | Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF) | — |
| Maximum Configuration Clock | 50 MHz | — |
| On-Chip Decompression | Yes (Altera compression algorithm) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | 3.0 V to 3.6 V (3.3 V typical) |
| 動作温度 | -40 °C to +85 °C (Industrial) | -40 C to +85 C (industrial / DM suffix) |
| パッケージ | 100-PQFP / 100-BQFP (20 x 14 mm) | 100-PQFP (20 x 14 mm) |
| ピン数 | 100 | — |
| 実装タイプ | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (per distributor listings) | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Multi-Device Daisy-Chain | Supported | — |
| Target FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Packaging | Tray | — |
| メモリタイプ | — | Non-volatile configuration PROM |
| インターフェース | — | Serial (Passive Serial / Passive Parallel Synchronous / Active Serial) |
| Maximum DCLK Frequency | — | 40 MHz |
| In-System Programming | — | Yes (IEEE 1149.1 / IEEE 1532 JTAG) |
| Cascade Support | — | Yes - two EPC8 devices for 16 Mb |
| MSLレベル | — | 1 (Unlimited) |
| RoHS ステータス | — | Compliant |
| Lead-Free / Halogen-Free | — | Lead-free (per supplier); halogen status not in datasheet excerpt |
| Compatible FPGA Families | — | Cyclone, Cyclone II, Cyclone III, Stratix, Arria |
| Configuration Modes | — | PS, PPS, AS (with appropriate FPGA master) |
| Programming Cycles | — | [DATA_NEEDED: minimum erase/write endurance cycles] |