EPM3512AFC256-21 vs EPM3512AFC256-20 比較
詳細な並列比較: EPM3512AFC256-21 メーカー: Altera および EPM3512AFC256-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 Obsolete仕様比較
| パラメータ | EPM3512AFC256-21 | EPM3512AFC256-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $9.75 |
| Device Family | MAX 3000A | — |
| Logic Elements / Macrocells | 512 macrocells | — |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 87 MHz | — |
| パッケージ | FBGA-256 (FineLine BGA) | 256-ball FBGA (Fine-pitch BGA) |
| 動作温度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Programmable Pins (max) | [DATA_NEEDED: maximum user I/O pin count] | — |
| Programming Interface | JTAG / IEEE Std. 1532 ISP | — |
| メモリタイプ | Non-volatile EPROM/EEPROM cell array | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| Typical Usable Gates | — | 10,000 |
| Speed Grade | — | -20 (20 ns tPD) |
| ピン数 | — | 256 |
| Operating Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| I/O Standards | — | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| JTAG Support | — | Yes (boundary-scan + ISP) |
| MSLレベル | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| Configuration Memory | — | Internal EEPROM |