EPM3512AQC208-7 vs EPM3512AQC208-10N 比較
詳細な並列比較: EPM3512AQC208-7 メーカー: Intel および EPM3512AQC208-10N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 Nrnd仕様比較
| パラメータ | EPM3512AQC208-7 | EPM3512AQC208-10N |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $41.72 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | Up to 10,000 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 116.3 MHz | — |
| User I/Os | 172 | 172 |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| パッケージ | 208-Pin PQFP (FQFP, gull-wing) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 動作温度 | 0 C to +70 C (commercial) | 0 C to 70 C (commercial) |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | — |
| Process Technology | CMOS EEPROM, 0.30 um | CMOS EEPROM |
| RoHS ステータス | Compliant | [DATA_NEEDED: RoHS status not in verified web data] |
| Lead-Free | Yes | — |
| Logic Array Blocks (LABs) | — | 16 |
| 電源電圧 | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |