EPM3512AQC208-7 vs EPM3512AQC208-10N Comparison
Detailed side-by-side comparison of EPM3512AQC208-7 by Intel and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndSpecification Comparison
| Parameter | EPM3512AQC208-7 | EPM3512AQC208-10N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $41.72 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | Up to 10,000 |
| Propagation Delay (tPD) | 7.5 ns | β |
| Counter Frequency (fCNT) | 116.3 MHz | β |
| User I/Os | 172 | 172 |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | β |
| Package | 208-Pin PQFP (FQFP, gull-wing) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to 70 C (commercial) |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | β |
| Process Technology | CMOS EEPROM, 0.30 um | CMOS EEPROM |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status not in verified web data] |
| Lead-Free | Yes | β |
| Logic Array Blocks (LABs) | β | 16 |
| Supply Voltage | β | 3.3 V |
| Pin-to-Pin Delay | β | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | β | 227.3 MHz |
| Speed Grade | β | -10 |
| In-System Programming | β | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | Built-in, IEEE 1149.1 compliant |
| I/O Standards | β | MultiVolt (1.8V / 2.5V / 3.3V) |