EPM5032DC-15 vs EPM5032DC-25 比較

詳細な並列比較: EPM5032DC-15 メーカー: Altera および EPM5032DC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5032DC-15 EPM5032DC-25
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete NRND
在庫状況 In Stock In Stock
単価(USD) $9.95 $3.55
Family MAX 5000 —
Device Type UV-erasable EPLD (PAL-type CMOS) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 600 —
Macrocells 32 32
Propagation Delay (tPD) 15 ns —
Maximum Toggle Frequency (fMAX) 83.3 MHz —
Supply Voltage (VCC) 5 V (nominal) —
Logic Family CMOS, TTL-compatible I/O —
Programmable Pins 16 bidirectional I/O + 4 dedicated input = 20 —
Total Package Pins 28 —
パッケージ CERDIP-28 (windowed, through-hole) CDIP-28 (Windowed Ceramic DIP-28)
実装タイプ Through-Hole (DIP) —
動作温度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Erasure Method UV light through ceramic quartz window UV light through ceramic window
Process Technology CMOS CMOS, EPROM (UV-Erasable)
RoHS ステータス [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Lead-Free unknown —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer

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