EPM5032DC-15 vs EPM5032DC-25 对比

详细并排对比 EPM5032DC-15 出自 Altera 和 EPM5032DC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032DC-15 EPM5032DC-25
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.95 $3.55
Family MAX 5000 —
Device Type UV-erasable EPLD (PAL-type CMOS) UV Erasable Programmable Logic Device (EPLD)
Usable Gates 600 —
Macrocells 32 32
Propagation Delay (tPD) 15 ns —
Maximum Toggle Frequency (fMAX) 83.3 MHz —
Supply Voltage (VCC) 5 V (nominal) —
Logic Family CMOS, TTL-compatible I/O —
Programmable Pins 16 bidirectional I/O + 4 dedicated input = 20 —
Total Package Pins 28 —
封装 CERDIP-28 (windowed, through-hole) CDIP-28 (Windowed Ceramic DIP-28)
安装类型 Through-Hole (DIP) —
工作温度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Erasure Method UV light through ceramic quartz window UV light through ceramic window
Process Technology CMOS CMOS, EPROM (UV-Erasable)
RoHS 状态 [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Lead-Free unknown —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer

数据手册与资源

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