EPM5032DI-20 vs EPM5032DM 比較
詳細な並列比較: EPM5032DI-20 メーカー: Intel および EPM5032DM メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DI-20 | EPM5032DM |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.75 | $15.90 |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| 最大クロック周波数 | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| パッケージ | Ceramic DIP-20 (windowed, UV-erasable) | CDIP-28 (ceramic windowed DIP, 28-pin) |
| 動作温度 | Industrial (per 'I' suffix) | -55C to +125C (military/extended, ceramic package) |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | Non-compliant (ceramic DIP with UV window) |
| Lead-Free | [DATA_NEEDED: lead-free status] | No (ceramic DIP contains lead) |
| Device Family | — | MAX 5000 |
| Propagation Delay (tPD) | — | 25 ns |
| Usable Gates | — | 600 to 1000 (typical) |
| Logic Inputs | — | 32 |
| Process Technology | — | CMOS EEPROM |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Standby Current | — | [DATA_NEEDED: ICC standby current] |
| Programming Technology | — | UV-erasable (windowed) EEPROM |
| Logic Function | — | Combinational and registered (synchronous) |
| Output Polarity | — | Programmable |
| Program Retention | — | Non-volatile (EEPROM) |
| 実装タイプ | — | Through-hole (DIP) |