EPM5032DI-25 vs EPM5032DC-20 比較

詳細な並列比較: EPM5032DI-25 メーカー: Altera および EPM5032DC-20 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5032DI-25 EPM5032DC-20
ブランド Altera Intel
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 NRND Obsolete
在庫状況 In Stock In Stock
単価(USD) $18.20 $5.05
Family MAX 5000 —
Device Type UV-erasable Programmable Logic Device (PLD) CPLD (Complex Programmable Logic Device)
Architecture PAL-type, CMOS, AND-OR sum-of-products —
Macrocells 32 32
Product Terms 320 —
Logic Gates [DATA_NEEDED: equivalent gate count] —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Array Inputs 24 —
Registered Outputs 16 —
Global Clocks 1 —
Propagation Delay (tPD) 25 ns —
Maximum Clock Frequency (fMAX) 62.5 MHz —
電源電圧 5 V —
Process Technology CMOS —
パッケージ Ceramic DIP, windowed (UV-erasable) 20-pin DIP (Windowed Ceramic, 0.3" wide)
ピン数 [DATA_NEEDED: exact pin count - 24 or 28] —
動作温度 0C to +70C (commercial) [DATA_NEEDED: commercial/industrial/military grade]
I/O Standard TTL-compatible —
Programmability UV-erasable, EPROM-based —
Development Tool MAX+PLUS II / A+PLUS —
RoHS ステータス [DATA_NEEDED: likely non-compliant due to ceramic DIP] Compliant (per IC-Components listing)
Lifecycle Not Recommended for New Designs (NRND) —
Product Family — MAX 5000
Programmable Technology — UV-Erasable / OTP EPROM
Usable Gates — 600
Maximum Frequency (fCNT) — 71.4 MHz
Pin-to-Pin Delay (tPD) — 20 ns
Speed Grade — -20
Supply Voltage (VCC) — 5 V
実装タイプ — Through-Hole
Logic Blocks — 4 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: I/O pin count for DIP-20 variant]
Lead Free — [DATA_NEEDED: confirmed lead-free]
Manufacturer — Altera (now Intel Programmable Solutions Group)
Programming Method — Altera MAX+PLUS II / Quartus (legacy support)

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