EPM5064LC-1 vs EPM5064LC-2 比較
詳細な並列比較: EPM5064LC-1 メーカー: Altera および EPM5064LC-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064LC-1 | EPM5064LC-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $8.40 |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1.25K (approx.) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Internal Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Input Lines | 36 | — |
| Dedicated Inputs | 7 | — |
| Output Lines | 28 | — |
| Programming Technology | OTP / UV-Erasable EPROM | — |
| パッケージ | 44-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-44 (J-Lead, plastic) |
| Process Technology | CMOS | CMOS, OTP EPROM (UV-erasable base) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not specified in source] |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Device Family | — | MAX 5000 |
| Logic Elements per LAB | — | 16 |
| Number of Inputs | — | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | — | 28 |
| Number of Flip-Flops | — | 28 |
| Maximum Internal Frequency | — | 40 MHz |
| Programmable Polarity | — | Yes |
| Programmable Output Enable | — | Yes, per macrocell |
| 実装タイプ | — | Surface Mount |
| Programming Method | — | Altera byte-wide / JTAG programmer |