EPM5192-1LC vs EPM5192AGC 比較

詳細な並列比較: EPM5192-1LC メーカー: Altera および EPM5192AGC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192-1LC EPM5192AGC
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $19.40 $56.00
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable / OTP Complex PLD (EPLD)
Usable Gates 3,750 —
Macrocells 192 192
Logic Array Blocks (LABs) 4 —
User I/O Pins 64 —
Maximum Operating Frequency 62.5 MHz —
Propagation Delay (tpd) [DATA_NEEDED: -1 speed grade tpd in ns] —
電源電圧 5 V [DATA_NEEDED: VCC nominal and tolerance]
Process Technology UV EPROM, erasable windowless CMOS
Programmable Interconnect PIA (Programmable Interconnect Array) —
JTAG Boundary Scan IEEE 1149.1 compliant —
パッケージ 64-pin Ceramic J-Lead Chip Carrier (LC) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
実装タイプ Surface Mount Through-hole (Pin Grid Array)
動作温度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
RoHS ステータス Non-compliant (ceramic windowless package, lead-bearing termination) Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

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