EPM5192-1LC vs EPM5192AGC 对比
详细并排对比 EPM5192-1LC 出自 Altera 和 EPM5192AGC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192-1LC | EPM5192AGC |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.40 | $56.00 |
| Family | MAX 5000 | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable / OTP Complex PLD (EPLD) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| 电源电压 | 5 V | [DATA_NEEDED: VCC nominal and tolerance] |
| Process Technology | UV EPROM, erasable windowless | CMOS |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| 封装 | 64-pin Ceramic J-Lead Chip Carrier (LC) | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| 安装类型 | Surface Mount | Through-hole (Pin Grid Array) |
| 工作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS 状态 | Non-compliant (ceramic windowless package, lead-bearing termination) | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Logic Density | — | High-density (per MAX 5000 family definition) |
| Architecture | — | CMOS, sum-of-products with macrocell output logic |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Programmability | — | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| Security Bit | — | Programmable security bit (per MAX 5000 family) |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |