EPM5192AGC-15 vs EPM5192AJC84-15 比較
詳細な並列比較: EPM5192AGC-15 メーカー: Altera および EPM5192AJC84-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete仕様比較
| パラメータ | EPM5192AGC-15 | EPM5192AJC84-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.80 | $18.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (typical for 192-macrocell MAX 5000) | — |
| Maximum User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| パッケージ | Ceramic Pin Grid Array (PGA) | 84-pin PLCC (J84C) windowed ceramic |
| Programming Method | UV erase + EPROM program (via Altera programmer) | UV-erase + EPROM programming (windowed package) |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS ステータス | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] | Non-compliant (contains Pb, ceramic windowed package) |
| ライフサイクル状態 | Obsolete / Last Time Buy (per Altera legacy product list) | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tpd) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 83.3 MHz |
| 実装タイプ | — | Surface Mount |
| Logic Blocks | — | 16 Logic Array Blocks (LABs) |
| I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Process Technology | — | CMOS EPROM |