EPM5192AGC-20 vs EPM5192AGC 比較

詳細な並列比較: EPM5192AGC-20 メーカー: Intel および EPM5192AGC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192AGC-20 EPM5192AGC
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $9.95 $56.00
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type EPLD (EEPLD, UV-erasable) UV-Erasable / OTP Complex PLD (EPLD)
Macrocells 192 192
Usable Gates 12,000 —
Propagation Delay (tPD) 20 ns —
Counter Frequency (fCNT) 100 MHz (max) —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Logic Array Blocks (LABs) 8 —
Dedicated I/O Pins 96 —
Programming Interface IEEE 1149.1 JTAG —
In-System Programmability Yes (5 V ISP) —
Security Bit Yes (pattern read-back protected) Programmable security bit (per MAX 5000 family)
パッケージ PGA-132 (ceramic windowed, 'GC') 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
実装タイプ Through-hole (PGA socket) Through-hole (Pin Grid Array)
動作温度 0C to 70C (commercial) [DATA_NEEDED: operating temperature range]
RoHS ステータス [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
電源電圧 — [DATA_NEEDED: VCC nominal and tolerance]
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

データシート&リソース

すべての製品を閲覧 BOMを作成 見積もり依頼