EPM5192AGC-20 vs EPM5192AGC 비교

다음의 상세 나란히 비교: EPM5192AGC-20 제조: Intel 및 EPM5192AGC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192AGC-20 EPM5192AGC
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $9.95 $56.00
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type EPLD (EEPLD, UV-erasable) UV-Erasable / OTP Complex PLD (EPLD)
Macrocells 192 192
Usable Gates 12,000 —
Propagation Delay (tPD) 20 ns —
Counter Frequency (fCNT) 100 MHz (max) —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Logic Array Blocks (LABs) 8 —
Dedicated I/O Pins 96 —
Programming Interface IEEE 1149.1 JTAG —
In-System Programmability Yes (5 V ISP) —
Security Bit Yes (pattern read-back protected) Programmable security bit (per MAX 5000 family)
패키지 PGA-132 (ceramic windowed, 'GC') 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
실장 유형 Through-hole (PGA socket) Through-hole (Pin Grid Array)
동작 온도 0C to 70C (commercial) [DATA_NEEDED: operating temperature range]
RoHS 상태 [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
공급 전압 — [DATA_NEEDED: VCC nominal and tolerance]
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청