EPM5192AGC-20 vs EPM5192AGC 对比
详细并排对比 EPM5192AGC-20 出自 Intel 和 EPM5192AGC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192AGC-20 | EPM5192AGC |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $56.00 |
| Family | MAX 5000 | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) |
| Device Type | EPLD (EEPLD, UV-erasable) | UV-Erasable / OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Counter Frequency (fCNT) | 100 MHz (max) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Logic Array Blocks (LABs) | 8 | — |
| Dedicated I/O Pins | 96 | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| In-System Programmability | Yes (5 V ISP) | — |
| Security Bit | Yes (pattern read-back protected) | Programmable security bit (per MAX 5000 family) |
| 封装 | PGA-132 (ceramic windowed, 'GC') | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) |
| 安装类型 | Through-hole (PGA socket) | Through-hole (Pin Grid Array) |
| 工作温度 | 0C to 70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS 状态 | [DATA_NEEDED: RoHS status - ceramic PGA windowed parts are typically pre-RoHS] | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) |
| Logic Density | — | High-density (per MAX 5000 family definition) |
| Architecture | — | CMOS, sum-of-products with macrocell output logic |
| Process Technology | — | CMOS |
| Speed Grade Suffix | — | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) |
| Programmability | — | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) |
| 电源电压 | — | [DATA_NEEDED: VCC nominal and tolerance] |
| Lifecycle | — | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) |
| Programming Support | — | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers |