EPM5192AJC-25 vs EPM5192AGC-15 比較
詳細な並列比較: EPM5192AJC-25 メーカー: Altera および EPM5192AGC-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192AJC-25 | EPM5192AGC-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.20 | $27.80 |
| Family | MAX 5000 EPLD | — |
| Manufacturer | Altera (now Intel PSG) | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tPD) | 25 ns | 15 ns (pin-to-pin, -15 speed grade) |
| パッケージ | PLCC-68 (windowed ceramic, AJC) | Ceramic Pin Grid Array (PGA) |
| ピン数 | 68 | — |
| 実装タイプ | Surface Mount | — |
| 電源電圧 | 5 V (typical) | — |
| Logic Blocks | MAX 5000 LABs (Logic Array Blocks) | — |
| Programmable Pins | [DATA_NEEDED: number of user I/O pins] | — |
| 動作温度 | [DATA_NEEDED: exact operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Erasure Method | UV-erasable (windowed ceramic package) | — |
| Programming Technology | EPROM (non-volatile) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| Military Grade | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | MAX 5000 |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 72 |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| ライフサイクル状態 | — | Obsolete / Last Time Buy (per Altera legacy product list) |