EPM5192GM-1 vs EPM5192GM 比較
詳細な並列比較: EPM5192GM-1 メーカー: Altera および EPM5192GM メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192GM-1 | EPM5192GM |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.80 | $58.00 |
| Family | MAX 5000 | — |
| Logic Cells | 192 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmable Element | UV-erasable EPROM | — |
| パッケージ | CPGA-84 (Windowed Ceramic PGA) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| ピン数 | 84 | — |
| 電源電圧 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: typical VCC range] |
| 動作温度範囲 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programmable Macrocells | 192 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| 実装タイプ | Through-Hole (Pin Grid Array socket) | Through-Hole (PGA) |
| RoHS Compliance | unknown (legacy ceramic PGA) | — |
| Lead-Free Status | unknown | — |
| Programming Interface | Altera ByteBlaster / JEDEC bitstream | JTAG-compatible (per MAX 5000 family) |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (PLD) |
| Technology | — | CMOS |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| 動作温度 | — | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS ステータス | — | Non-compliant (contains lead in ceramic PGA) |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |