EPM5192GM-1 vs EPM5192GM 비교
다음의 상세 나란히 비교: EPM5192GM-1 제조: Altera 및 EPM5192GM 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192GM-1 | EPM5192GM |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $27.80 | $58.00 |
| Family | MAX 5000 | — |
| Logic Cells | 192 | — |
| Propagation Delay (tpd) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmable Element | UV-erasable EPROM | — |
| 패키지 | CPGA-84 (Windowed Ceramic PGA) | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| 핀 수 | 84 | — |
| 공급 전압 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: typical VCC range] |
| 동작 온도 범위 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programmable Macrocells | 192 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| 실장 유형 | Through-Hole (Pin Grid Array socket) | Through-Hole (PGA) |
| RoHS Compliance | unknown (legacy ceramic PGA) | — |
| Lead-Free Status | unknown | — |
| Programming Interface | Altera ByteBlaster / JEDEC bitstream | JTAG-compatible (per MAX 5000 family) |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (PLD) |
| Technology | — | CMOS |
| Number of Macrocells | — | 192 |
| Usable Gates | — | 3,750 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | — | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | — | 55 ns |
| Erasure Method | — | UV (windowed ceramic package) |
| Maximum User I/O | — | [DATA_NEEDED: exact I/O count for CPGA-84] |
| 동작 온도 | — | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS 상태 | — | Non-compliant (contains lead in ceramic PGA) |
| Process Node | — | [DATA_NEEDED: CMOS process geometry] |