EPM5192JC68 vs EPM5192JC-ES 比較
詳細な並列比較: EPM5192JC68 メーカー: Altera および EPM5192JC-ES メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JC68 | EPM5192JC-ES |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.85 | $16.45 |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Elements / Macrocells | 192 macrocells | — |
| User I/O Pins | 76 | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| ピン数 | 68 | — |
| Package Type | PLCC-68 (J-Lead) | — |
| 動作温度 | 0C to 70C (commercial, JC suffix) | [DATA_NEEDED: operating temperature range for ES grade] |
| 電源電圧 | [DATA_NEEDED: VCC] | [DATA_NEEDED: VCC nominal] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX] | — |
| Configuration Memory | UV-Erasable EPROM | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Programmable Interconnect | Programmable Logic Array + Macrocells | — |
| Dedicated Inputs | 12 | — |
| Clock Pins | 4 dedicated | — |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Programming Tool | MAX+PLUS II (legacy) | — |
| Device Type | — | CPLD (EPLD) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| パッケージ | — | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSLレベル | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |