EPM5192JM vs EPM5192GM883B-2 比較
詳細な並列比較: EPM5192JM メーカー: Altera および EPM5192GM883B-2 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192JM | EPM5192GM883B-2 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $171.00 | $142.00 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | CPLD (Complex Programmable Logic Device), UV-erasable |
| Macrocells | 192 | 192 |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Total Input Channels | 72 | — |
| Propagation Delay (tPD) | 55 ns | 45 ns (-2 speed grade) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Technology | CMOS, UV-erasable | 5 V CMOS |
| パッケージ | 84-pin Ceramic JLCC with quartz window (J84) | 84-pin Ceramic Pin Grid Array (CPGA), code S-CPGA-P84 |
| 動作温度範囲 | -55 C to +125 C (military grade, 'M' suffix) | — |
| Logic Architecture | Shared product-term AND/OR, programmable polarity | — |
| Programming Method | UV erase + EPROM programmer, JEDEC map | — |
| Development Tool | MAX+PLUS II (legacy Altera toolchain) | — |
| Compliance | MIL-STD-883 processing available on /883B suffix variants | — |
| Maximum Internal Clock Frequency | — | 33.3 MHz |
| Supply Voltage (VCC, nominal) | — | 5 V |
| User I/O Pins | — | 64 |
| Package Outline | — | 28.45 mm square (approx.) |
| Military Screening | — | MIL-STD-883 (per '883' suffix) |
| 実装タイプ | — | Through-hole PGA socket |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |
| RoHS ステータス | — | non_compliant (ceramic CPGA with MIL-STD-883 screening) |
| JEDEC Package Code | — | S-CPGA-P84 |