EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
部品番号: EPM7128AETI100-7 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $46.25 | $46.25 |
| 10 | $41.63 | $416.30 |
| 100 | $37.21 | $3,721.00 |
| 500 | $33.5 | $16,750.00 |
| 1,000 | $30.1 | $30,100.00 |
EPM7128AETI100-7 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile digital integrated circuit that combines the instant-on, deterministic timing of PAL/GAL architecture with higher logic density and I/O count. Within the broader taxonomy, CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs: they offer faster, predictable timing than FPGAs at the cost of lower logic density, and they boot instantly without external configuration memory. The MAX 7000A family targets glue-logic, bus-interface, state-machine, and power-sequencing applications where deterministic propagation delay matters more than raw LUT count.
Key differentiating features of the EPM7128AETI100-7 include the MultiVolt I/O interface, which allows the device core to operate at 3.3 V while I/O banks interface with 2.5 V, 3.3 V, or 5 V systems; four dedicated inputs for global clock/clear/preset; and a Joint Test Action Group (JTAG) IEEE 1149.1 boundary-scan test interface for board-level testability. The -7 speed grade delivers 7.5 ns tPD, while the -10 grade trades speed for lower cost, and the -7N suffix denotes lead-free / RoHS compliance. The industrial temperature range (-40 C to +85 C) makes this part suitable for industrial controls, telecommunications infrastructure, and white-goods electronics.
The internal architecture uses a programmable interconnect array that routes signals between the Logic Array Blocks (LABs), each of which contains 16 macrocells with configurable product-term logic, flip-flops, and sharing expanders. This structure yields deterministic, deterministic propagation delay independent of routing complexity, a hallmark of CPLD timing closure.
Typical applications include bus-interface bridging (e.g., 8-bit/16-bit microprocessor-to-peripheral glue logic), address decoding, state-machine controllers, LED display multiplexing, and power-supply sequencing in industrial, automotive aftermarket, and telecom systems. Designers choose the EPM7128AETI100-7 specifically when they need a 5 V-tolerant 3.3 V core device in a 100-pin TQFP footprint that fits legacy board layouts migrated from earlier MAX 7000S (5 V) devices.
When designing with this device, ensure that I/O banks are powered from rails matching the MultiVolt specification of the external logic, and place 0.1 uF and 1 uF decoupling capacitors within 5 mm of each VCCIO/VCCINT pin pair. For JTAG programming, dedicate four general-purpose I/Os as TMS, TCK, TDI, and TDO if boundary-scan test access is required in production.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM7128AETI100-7 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128AETI100-7 （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Family, Process Technology, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128AETI100-7N
✅ ドロップイン✓ 在庫あり
$28.5 / 個
データシートを見る →EPM7128AETC100-7N
✅ ドロップイン✓ 在庫あり
$31.8 / 個
データシートを見る →EPM7128AETC100-7N
✅ ドロップイン✓ 在庫あり
$31.8 / 個
データシートを見る →EPM7128AETC100-10N
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7128AET1100-7
✅ ドロップイン✓ 在庫あり
$16.4 / 個
データシートを見る →EPM7128AETI100-7 最大定格＆電気的特性
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 84 |
| Logic Blocks (LABs) | 8 |
| Pin-to-Pin Delay (tPD) | 7.5 ns |
| Maximum Counter Frequency | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | 3.3 V |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | 4 dedicated |
| パッケージ | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| 動作温度 | -40 C to +85 C (Industrial) |
| 実装タイプ | Surface Mount |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |
EPM7128AETI100-7 ピン構成
| ピン 1 | I/O — User I/O pin (Bank 1) |
| ピン 2 | I/O — User I/O pin (Bank 1) |
| ピン 3 | I/O — User I/O pin (Bank 1) |
| ピン 4 | I/O — User I/O pin (Bank 1) |
| ピン 5 | I/O — User I/O pin (Bank 1) |
| ピン 6 | I/O — User I/O pin (Bank 1) |
| ピン 7 | I/O — User I/O pin (Bank 1) |
| ピン 8 | I/O — User I/O pin (Bank 1) |
| ピン 9 | I/O — User I/O pin (Bank 1) |
| ピン 10 | I/O — User I/O pin (Bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (Bank 1) |
| ピン 13 | I/O — User I/O pin (Bank 1) |
| ピン 14 | I/O — User I/O pin (Bank 1) |
| ピン 15 | I/O — User I/O pin (Bank 1) |
| ピン 16 | TDI — JTAG Test Data In |
| ピン 17 | TMS — JTAG Test Mode Select |
| ピン 18 | TCK — JTAG Test Clock |
| ピン 19 | TDO — JTAG Test Data Out |
| ピン 20 | GND — Ground |
| ピン 21 | VCCINT — Core supply voltage (3.3 V) |
| ピン 22 | I/O — User I/O pin (Bank 1) |
| ピン 23 | I/O — User I/O pin (Bank 1) |
| ピン 24 | I/O — User I/O pin (Bank 2) |
| ピン 25 | I/O — User I/O pin (Bank 2) |
| ピン 26 | I/O — User I/O pin (Bank 2) |
| ピン 27 | I/O — User I/O pin (Bank 2) |
| ピン 28 | I/O — User I/O pin (Bank 2) |
| ピン 29 | I/O — User I/O pin (Bank 2) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O pin (Bank 2) |
| ピン 32 | I/O — User I/O pin (Bank 2) |
| ピン 33 | I/O — User I/O pin (Bank 2) |
| ピン 34 | I/O — User I/O pin (Bank 2) |
| ピン 35 | I/O — User I/O pin (Bank 2) |
| ピン 36 | I/O — User I/O pin (Bank 2) |
| ピン 37 | I/O — User I/O pin (Bank 2) |
| ピン 38 | I/O — User I/O pin (Bank 2) |
| ピン 39 | GND — Ground |
| ピン 40 | I/O — User I/O pin (Bank 2) |
| ピン 41 | I/O — User I/O pin (Bank 2) |
| ピン 42 | I/O — User I/O pin (Bank 2) |
| ピン 43 | I/O — User I/O pin (Bank 3) |
| ピン 44 | I/O — User I/O pin (Bank 3) |
| ピン 45 | I/O — User I/O pin (Bank 3) |
| ピン 46 | I/O — User I/O pin (Bank 3) |
| ピン 47 | I/O — User I/O pin (Bank 3) |
| ピン 48 | I/O — User I/O pin (Bank 3) |
| ピン 49 | I/O — User I/O pin (Bank 3) |
| ピン 50 | GND — Ground |
| ピン 51 | INPUT/GCLK1 — Global Clock 1 input |
| ピン 52 | INPUT/GCLK3 — Global Clock 3 input |
| ピン 53 | INPUT/OE1 — Global OE 1 input |
| ピン 54 | INPUT/GCLRn — Global Clear input |
| ピン 55 | INPUT/OE2/GCLK2 — Global OE 2 / Global Clock 2 input |
| ピン 56 | INPUT/GCLK4 — Global Clock 4 input |
| ピン 57 | I/O — User I/O pin (Bank 3) |
| ピン 58 | I/O — User I/O pin (Bank 3) |
| ピン 59 | I/O — User I/O pin (Bank 3) |
| ピン 60 | VCCIO1 — Bank 1 I/O supply (2.5/3.3/5 V) |
| ピン 61 | I/O — User I/O pin (Bank 3) |
| ピン 62 | I/O — User I/O pin (Bank 3) |
| ピン 63 | I/O — User I/O pin (Bank 3) |
| ピン 64 | I/O — User I/O pin (Bank 3) |
| ピン 65 | I/O — User I/O pin (Bank 3) |
| ピン 66 | I/O — User I/O pin (Bank 3) |
| ピン 67 | I/O — User I/O pin (Bank 3) |
| ピン 68 | I/O — User I/O pin (Bank 3) |
| ピン 69 | I/O — User I/O pin (Bank 3) |
| ピン 70 | I/O — User I/O pin (Bank 3) |
| ピン 71 | I/O — User I/O pin (Bank 3) |
| ピン 72 | I/O — User I/O pin (Bank 3) |
| ピン 73 | I/O — User I/O pin (Bank 4) |
| ピン 74 | I/O — User I/O pin (Bank 4) |
| ピン 75 | GND — Ground |
| ピン 76 | VCCIO2 — Bank 2 I/O supply (2.5/3.3/5 V) |
| ピン 77 | I/O — User I/O pin (Bank 4) |
| ピン 78 | I/O — User I/O pin (Bank 4) |
| ピン 79 | I/O — User I/O pin (Bank 4) |
| ピン 80 | I/O — User I/O pin (Bank 4) |
| ピン 81 | I/O — User I/O pin (Bank 4) |
| ピン 82 | I/O — User I/O pin (Bank 4) |
| ピン 83 | I/O — User I/O pin (Bank 4) |
| ピン 84 | I/O — User I/O pin (Bank 4) |
| ピン 85 | I/O — User I/O pin (Bank 4) |
| ピン 86 | GND — Ground |
| ピン 87 | I/O — User I/O pin (Bank 4) |
| ピン 88 | I/O — User I/O pin (Bank 4) |
| ピン 89 | I/O — User I/O pin (Bank 4) |
| ピン 90 | I/O — User I/O pin (Bank 4) |
| ピン 91 | I/O — User I/O pin (Bank 4) |
| ピン 92 | I/O — User I/O pin (Bank 1) |
| ピン 93 | I/O — User I/O pin (Bank 1) |
| ピン 94 | I/O — User I/O pin (Bank 1) |
| ピン 95 | VCCIO3 — Bank 3 I/O supply (2.5/3.3/5 V) |
| ピン 96 | I/O — User I/O pin (Bank 1) |
| ピン 97 | I/O — User I/O pin (Bank 1) |
| ピン 98 | I/O — User I/O pin (Bank 1) |
| ピン 99 | I/O — User I/O pin (Bank 1) |
| ピン 100 | I/O — User I/O pin (Bank 1) |
主な用途
EPM7128AETI100-7 の用途: 6 件s: Industrial Bus Interface / Glue Logic, Address Decoding and Chip-Select Generation, State-Machine Controller for Power Sequencing, Legacy Peripheral Emulation and Bus Translation, LED Display Multiplexing and Panel Controllers, Telecom Line-Card Glue Logic.
Industrial Bus Interface / Glue Logic
The EPM7128AETI100-7's 128 macrocells and 84 user I/Os make it well-suited for bridging between microcontrollers, ASICs, and peripheral buses in industrial controllers. Its 7.5 ns pin-to-pin delay (tPD) keeps address decoding and chip-select generation deterministic, which is critical when the CPLD sits between an 80 MHz 32-bit MCU and asynchronous SRAM or peripheral FIFOs. MultiVolt I/O allows direct 5 V-3.3 V level shifting within the same device, eliminating external translator ICs. Designers commonly instantiate the EPM7128AETI100-7 in PLC backplanes, motor-control boards, and industrial sensor hubs where deterministic timing and legacy 5 V bus compatibility are required simultaneously.
おすすめ
Address Decoding and Chip-Select Generation
The EPM7128AETI100-7's deterministic 7.5 ns tPD and 128 macrocells provide ample capacity to decode wide address buses (24-32 bits) and generate multiple chip-select strobes for memory banks, peripherals, and external ASICs. Because CPLD propagation delay is independent of routing complexity, a deeply nested decode tree still completes within the -7 timing budget. The MultiVolt I/O interface lets the CPLD directly drive 5 V SRAM chips while running its core at 3.3 V, removing the level-shifters that would otherwise sit in the CS path. Industrial embedded boards and telecom line cards historically relied on this part for memory-map decoding before FPGAs displaced CPLDs in greenfield designs.
おすすめ
State-Machine Controller for Power Sequencing
Power-supply sequencers benefit from the EPM7128AETI100-7's non-volatile EEPROM configuration: the state machine boots instantly at POR with no FPGA-style configuration delay, enabling strict rail-to-rail sequencing in multi-rail systems. Designers build multi-state FSMs across the 8 LABs to sequence 3.3 V core, 1.8 V DDR, 1.0 V FPGA, and 5 V analog rails with programmable delays. The four dedicated global clock/clear/preset inputs double as hardware watchdog timers and power-good triggers. The industrial -40 C to +85 C temperature range makes this part acceptable for telecom shelf-power controllers and factory-floor PLC power sub-systems.
おすすめ
Legacy Peripheral Emulation and Bus Translation
The EPM7128AETI100-7 is widely used to emulate older ISA-bus peripherals, SCSI controllers, or VME-bus interfaces on modern motherboards where the original logic chips have been discontinued. Its 128 macrocells can model decades-old glue-logic ASICs while presenting JTAG for board-test access. The JTAG IEEE 1149.1 boundary-scan interface also doubles as a board-level test access port (TAP), invaluable in production test for legacy aerospace, defense, and industrial-control boards where traceability is mandatory. Migration programs that need to extend the lifecycle of 1990s industrial PCs and telecom switches still source this part for board-repair and low-volume rebuilds.
おすすめ
LED Display Multiplexing and Panel Controllers
Large LED-matrix displays and dot-matrix panels require high-frequency row-scanning and column-refresh logic that benefits from the EPM7128AETI100-7's 129.9 MHz counter frequency and 84 I/Os. Each LAB can drive a column decoder while the global clocks drive the row scanner, producing flicker-free refresh at 1 kHz or higher without burdening the host MCU. The MultiVolt I/O supports direct LED-driver interfaces (e.g., 5 V TPIC6B595 shift registers) alongside 3.3 V microcontrollers. Stadium scoreboards, traffic signs, and factory-floor HMI panels from the early 2000s frequently used this part for its deterministic refresh timing and instant-on non-volatile boot.
おすすめ
Telecom Line-Card Glue Logic
Telecom line cards aggregate TDM, HDLC, and ATM traffic onto backplane buses, requiring deterministic timing, bus-arbitration logic, and multi-voltage I/O - exactly the EPM7128AETI100-7's design center. The MAX 7000A architecture's instant-on EEPROM boot makes this part ideal for hot-swap line-card designs where configuration must complete within a 100 ms insertion window. MultiVolt I/O handles the mix of 5 V and 3.3 V bus interfaces on legacy line cards. The industrial -40 C to +85 C range tolerates the airflow-restricted, elevated-temperature environments of central-office equipment cabinets. Long-lifecycle telecom integrators still maintain stock for repair purposes even though the part is officially obsolete.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128AETI100-7 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128AETI100-7N | EPM7128AETC100-7 | EPM7128AETC100-7N | EPM7128AETC100-10N | EPM7128AET1100-7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns | 10 ns (-33%) | 7.5 ns |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Maximum Counter Frequency | 129.9 MHz | 129.9 MHz | 129.9 MHz | 129.9 MHz | 100 MHz (lower grade) | 129.9 MHz |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 |
| User I/Os | 84 | 84 | 84 | 84 | 84 | 84 |
主な差別化要因
- Industrial temperature range with 7.5 ns tPD （vs EPM7128AETC100-7)
- Faster speed grade （vs EPM7128AETC100-10N)
- MultiVolt I/O supports mixed-voltage systems （vs EPM7128AETI100-10)
設計ノート
Provide separate, well-decoupled supplies for VCCINT (3.3 V core) and each VCCIO bank (2.5 V, 3.3 V, or 5 V). Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCCINT and VCCIO pin pair, supplemented by a single 10 uF bulk capacitor per supply rail. Power sequencing is not required because the EEPROM configuration boots instantaneously at POR, but ramp rates should remain within the datasheet's 50 V/ms limit.
Route JTAG signals TMS, TCK, TDI, and TDO as a matched-length group with 4.7 kohm pull-ups on TMS and TDI to VCCIO1. Keep the JTAG chain out of the path of fast-edge signals from clock-output I/Os to avoid noise coupling into the TAP. Use the dedicated GCLK1-GCLK4 inputs for high-frequency clocks rather than routing clocks through general-purpose I/Os to preserve signal integrity.
Do not mix 5 V and 3.3 V I/O banks that share the same JTAG chain without buffering - level mismatch can damage the JTAG drivers. Always use the Quartus II Programmer (or compatible third-party programmer such as the BPM Microsystems) to program the EEPROM; in-circuit ISP works only if VCCINT is stable and JTAG pull-ups are present. Confirm that the -7 speed grade meets your timing budget before substituting a -10 grade; the slower part may violate set-up/hold requirements in high-frequency designs.
The EPM7128AETI100-7 in TQFP-100 typically dissipates under 1 W at full I/O toggle activity across all 84 outputs. The exposed thermal pad is not present on the TQFP-100 package, so board-level thermal relief comes from copper pours on the top and inner layers. For designs with continuous high-frequency I/O switching (e.g., 50 MHz+), ensure at least 1 square inch of ground copper is connected to GND pins 11, 20, 30, 39, 50, 75, and 86 to keep junction temperature below 125 C at the 85 C ambient upper bound.
コンプライアンス情報
EPM7128AETI100-7 (non-N suffix) uses tin-lead finish and is not RoHS compliant. The -7N variant is the lead-free RoHS-compliant version. Industrial temperature grade is -40C to +85C. AEC-Q100 not applicable as CPLDs are not automotive-qualified. REACH and conflict-mineral declarations not stated in the public datasheet.
