EPM7128SQC100-10N vs EPM7128SQC100-7F 比較
詳細な並列比較: EPM7128SQC100-10N メーカー: Altera および EPM7128SQC100-7F メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7128SQC100-10N | EPM7128SQC100-7F |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.95 | $9.75 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| パッケージ | 100-pin PQFP (BQFP) | 100-pin PQFP (SQC100), surface-mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| 動作温度 | -40C to +85C (industrial) | 0 °C to 70 °C (Commercial) |
| 実装タイプ | Surface Mount | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Logic Elements / Blocks | — | 8 LABs |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Maximum Operating Frequency | — | 125 MHz |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Number of User I/O | — | 84 |
| Programmable Type | — | In-System Programmable (ISP), EEPROM |
| JTAG Boundary-Scan | — | Yes (IEEE 1149.1 BST) |
| Open-Drain Output Option | — | Yes |
| Lead-Free (Pb-Free) | — | Yes (matte-tin, '-F' suffix) |
| RoHS ステータス | — | [DATA_NEEDED: confirmed from manufacturer] |
| メモリタイプ | — | Non-volatile (EEPROM configuration) |