EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
部品番号: EPM7128SQC100-10N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $22.55 | $22.55 |
| 10 | $20.5 | $205.00 |
| 100 | $18.25 | $1,825.00 |
| 500 | $16.4 | $8,200.00 |
| 1,000 | $14.95 | $14,950.00 |
EPM7128SQC100-10N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of a PAL (Programmable Array Logic) with the density of an FPGA. CPLDs occupy a position in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic -> semiconductor. They are valued for their deterministic timing, instant-on non-volatile configuration (EEPROM-based in the MAX 7000 family), and low power consumption, making them ideal for glue logic, bus interfacing, and state-machine implementation in industrial, telecommunications, and embedded systems.
Key features of the EPM7128SQC100-10N include 128 macro cells organized as 8 Logic Array Blocks (LABs) of 16 macro cells each, 84 user I/O pins, 5V core supply with 3.3V or 5V I/O compatibility via MultiVolt interface, in-system programmability (ISP) via the JTAG-compliant 4-pin IEEE Std. 1149.1 interface, and 10ns combinatorial propagation delay (tPD). The MAX 7000 architecture is built on Altera's second-generation MAX architecture with EEPROM configuration memory.
From a technical depth perspective, the MAX 7000 family uses a programmable interconnect array (PIA) that routes signals between LABs without contention, and each macro cell contains a programmable AND/OR array, a product-term select matrix, and a configurable flip-flop. The device supports JTAG boundary-scan testing per IEEE 1149.1 and includes built-in test logic for board-level verification. The 100-pin PQFP package has a body size of approximately 20 x 14 mm with 0.65 mm pitch gull-wing leads.
Typical applications include industrial control glue logic, address decoding and bus interfacing in embedded systems, state machines for motor control, peripheral interfacing in telecommunications equipment, and legacy 5V system designs where FPGAs are overkill. The wide operating voltage tolerance (4.75V to 5.25V) also supports -40C to +85C industrial temperature range operation.
When designing with this device, ensure the JTAG chain is properly terminated to avoid programming failures, and use the Quartus Prime or MAX+PLUS II software for design entry, synthesis, and programming file generation. Power sequencing should maintain VCC within specification before JTAG operations to prevent partial configuration.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM7128SQC100-10N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128SQC100-10N （同一形状・フットプリント） — 相違点: Package, RoHS Status, Family, Operating Temperature, Logic Array Blocks (LABs).
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128SQC100-10F
✅ ドロップイン✓ 在庫あり
$4.95 / 個
データシートを見る →EPM7128SQC100-10
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM7128AETC100-10N
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7128AETC100-10
✅ ドロップイン✓ 在庫あり
$13.85 / 個
データシートを見る →EPM7128BTC100-10
✅ ドロップイン✓ 在庫あり
$11.2 / 個
データシートを見る →EPM7128SQC100-10N 最大定格＆電気的特性
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) |
| User I/O Pins | 84 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency | 100 MHz |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) |
| パッケージ | 100-pin PQFP (BQFP) |
| Configuration Memory | EEPROM (non-volatile) |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin |
| 動作温度 | -40C to +85C (industrial) |
| 実装タイプ | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) |
| Architecture Generation | Second-generation MAX |
EPM7128SQC100-10N ピン構成
| ピン 1 | I/O — User I/O pin (general purpose) |
| ピン 2 | I/O — User I/O pin (general purpose) |
| ピン 3 | I/O — User I/O pin (general purpose) |
| ピン 4 | I/O — User I/O pin (general purpose) |
| ピン 5 | I/O — User I/O pin (general purpose) |
| ピン 6 | I/O — User I/O pin (general purpose) |
| ピン 7 | I/O — User I/O pin (general purpose) |
| ピン 8 | I/O — User I/O pin (general purpose) |
| ピン 9 | VCC — 5V supply |
| ピン 10 | I/O — User I/O pin (general purpose) |
| ピン 11 | I/O — User I/O pin (general purpose) |
| ピン 12 | GND — Ground |
| ピン 13 | I/O — User I/O pin (general purpose) |
| ピン 14 | I/O — User I/O pin (general purpose) |
| ピン 15 | I/O — User I/O pin (general purpose) |
| ピン 16 | I/O — User I/O pin (general purpose) |
| ピン 17 | I/O — User I/O pin (general purpose) |
| ピン 18 | I/O — User I/O pin (general purpose) |
| ピン 19 | I/O — User I/O pin (general purpose) |
| ピン 20 | I/O — User I/O pin (general purpose) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin (general purpose) |
| ピン 23 | I/O — User I/O pin (general purpose) |
| ピン 24 | I/O — User I/O pin (general purpose) |
| ピン 25 | I/O — User I/O pin (general purpose) |
| ピン 26 | I/O — User I/O pin (general purpose) |
| ピン 27 | I/O — User I/O pin (general purpose) |
| ピン 28 | VCC — 5V supply |
| ピン 29 | I/O — User I/O pin (general purpose) |
| ピン 30 | I/O — User I/O pin (general purpose) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin (general purpose) |
| ピン 33 | I/O — User I/O pin (general purpose) |
| ピン 34 | I/O — User I/O pin (general purpose) |
| ピン 35 | I/O — User I/O pin (general purpose) |
| ピン 36 | I/O — User I/O pin (general purpose) |
| ピン 37 | I/O — User I/O pin (general purpose) |
| ピン 38 | I/O — User I/O pin (general purpose) |
| ピン 39 | I/O — User I/O pin (general purpose) |
| ピン 40 | I/O — User I/O pin (general purpose) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (general purpose) |
| ピン 43 | I/O — User I/O pin (general purpose) |
| ピン 44 | I/O — User I/O pin (general purpose) |
| ピン 45 | I/O — User I/O pin (general purpose) |
| ピン 46 | I/O — User I/O pin (general purpose) |
| ピン 47 | I/O — User I/O pin (general purpose) |
| ピン 48 | VCC — 5V supply |
| ピン 49 | I/O — User I/O pin (general purpose) |
| ピン 50 | I/O — User I/O pin (general purpose) |
| ピン 51 | GND — Ground |
| ピン 52 | INPUT/GCLK — Global clock input / dedicated input |
| ピン 53 | INPUT/OE2 — Output enable 2 / dedicated input |
| ピン 54 | INPUT/OE1 — Output enable 1 / dedicated input |
| ピン 55 | INPUT/CLR — Clear / dedicated input |
| ピン 56 | I/O — User I/O pin (general purpose) |
| ピン 57 | I/O — User I/O pin (general purpose) |
| ピン 58 | I/O — User I/O pin (general purpose) |
| ピン 59 | I/O — User I/O pin (general purpose) |
| ピン 60 | I/O — User I/O pin (general purpose) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — User I/O pin (general purpose) |
| ピン 63 | I/O — User I/O pin (general purpose) |
| ピン 64 | I/O — User I/O pin (general purpose) |
| ピン 65 | I/O — User I/O pin (general purpose) |
| ピン 66 | I/O — User I/O pin (general purpose) |
| ピン 67 | I/O — User I/O pin (general purpose) |
| ピン 68 | I/O — User I/O pin (general purpose) |
| ピン 69 | VCC — 5V supply |
| ピン 70 | I/O — User I/O pin (general purpose) |
| ピン 71 | I/O — User I/O pin (general purpose) |
| ピン 72 | GND — Ground |
| ピン 73 | I/O — User I/O pin (general purpose) |
| ピン 74 | I/O — User I/O pin (general purpose) |
| ピン 75 | I/O — User I/O pin (general purpose) |
| ピン 76 | I/O — User I/O pin (general purpose) |
| ピン 77 | I/O — User I/O pin (general purpose) |
| ピン 78 | I/O — User I/O pin (general purpose) |
| ピン 79 | I/O — User I/O pin (general purpose) |
| ピン 80 | I/O — User I/O pin (general purpose) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — User I/O pin (general purpose) |
| ピン 83 | I/O — User I/O pin (general purpose) |
| ピン 84 | I/O — User I/O pin (general purpose) |
| ピン 85 | I/O — User I/O pin (general purpose) |
| ピン 86 | I/O — User I/O pin (general purpose) |
| ピン 87 | I/O — User I/O pin (general purpose) |
| ピン 88 | VCC — 5V supply |
| ピン 89 | I/O — User I/O pin (general purpose) |
| ピン 90 | I/O — User I/O pin (general purpose) |
| ピン 91 | GND — Ground |
| ピン 92 | I/O — User I/O pin (general purpose) |
| ピン 93 | TDI — JTAG Test Data In |
| ピン 94 | TMS — JTAG Test Mode Select |
| ピン 95 | TCK — JTAG Test Clock |
| ピン 96 | TDO — JTAG Test Data Out |
| ピン 97 | I/O — User I/O pin (general purpose) |
| ピン 98 | I/O — User I/O pin (general purpose) |
| ピン 99 | I/O — User I/O pin (general purpose) |
| ピン 100 | I/O — User I/O pin (general purpose) |
主な用途
EPM7128SQC100-10N の用途: 6 件s: Industrial Control Glue Logic, Address Decoding and Bus Interfacing, Telecommunications Equipment Logic, Legacy 5V System Designs, State Machine and FSM Implementation, Peripheral Interfacing Bridges.
Industrial Control Glue Logic
The EPM7128SQC100-10N serves as deterministic glue logic in industrial PLC and motor-control systems, where its 128 macro cells, 84 user I/Os, and 10ns tPD meet the timing requirements for bus arbitration and signal conditioning. The instant-on non-volatile EEPROM configuration eliminates boot time and external PROM, while the -40C to +85C industrial temperature range supports factory-floor operation. Place the CPLD between a microcontroller and peripheral bus to implement custom decode, latch, and handshake logic with deterministic pin-to-pin delay - critical for hard-real-time control loops where FPGA variability would be unacceptable.
おすすめ
Address Decoding and Bus Interfacing
In embedded CPU systems, the EPM7128SQC100-10N implements address decoding and peripheral chip-select generation with 10ns propagation delay, well within typical 8/16-bit microcontroller bus cycles. The 128 macro cells comfortably handle complex decode trees across multiple peripheral devices, while the MultiVolt I/O interface connects directly to 3.3V MCUs without level shifters. Each LAB (Logic Array Block) of 16 macro cells can be assigned to a separate peripheral bus, and the deterministic tPD ensures zero-wait-state operation across the full industrial temperature range.
おすすめ
Telecommunications Equipment Logic
The EPM7128SQC100-10N provides non-volatile, deterministic logic for telecommunications line cards and backplane controllers where instant-on behavior is essential. Its 84 I/Os are well suited to LVCMOS or TTL-level backplane signaling, and the JTAG interface per IEEE 1149.1 enables board-level boundary-scan testing to verify interconnect integrity during manufacturing. The 5V supply tolerance (4.75V to 5.25V) aligns with traditional telecom -48V isolated supply rails, and the 10ns tPD supports legacy telecom timing budgets at line-card interface speeds.
おすすめ
Legacy 5V System Designs
For systems requiring 5V core operation (such as legacy ISA-bus cards, VME boards, or older industrial controllers), the EPM7128SQC100-10N provides 128 macro cells at 5V VCCINT with 3.3V/5V tolerant I/Os via MultiVolt. Most modern FPGAs operate only at lower core voltages and cannot interface directly to 5V systems without level shifters, making the CPLD the right choice. The non-volatile EEPROM configuration also eliminates the boot PROM required by SRAM-based FPGAs, reducing BOM cost and board area in legacy designs.
おすすめ
State Machine and FSM Implementation
The EPM7128SQC100-10N implements complex state machines for protocol converters, sequencers, and control logic with deterministic timing that FPGA block-RAM-driven FSMs cannot match. Each macro cell contains a programmable flip-flop and product-term select matrix, supporting one-hot, binary, or Gray-coded state machines with 10ns clock-to-output delay. The 100 MHz fMAX supports high-speed protocol conversion in serial-communication bridges, while 84 I/Os accommodate multi-channel state machines in parallel control systems.
おすすめ
Peripheral Interfacing Bridges
The EPM7128SQC100-10N bridges mismatched peripherals in mixed-voltage systems, converting 5V parallel buses to 3.3V SPI or vice versa. Its 84 user I/Os and MultiVolt interface handle wide parallel buses (up to 32-bit data plus control signals) with 10ns propagation delay. The EEPROM configuration is non-volatile, so bridges survive power cycles without reconfiguration, and JTAG boundary-scan simplifies production testing of bridge-equipped boards. The 100-pin PQFP package provides sufficient I/O for full 32-bit bridging with handshake lines.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128SQC100-10N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128SQC100-10F | EPM7128SQC100-10 | EPM7128AETC100-10N | EPM7128AETC100-10 | EPM7128BTC100-10 |
|---|---|---|---|---|---|---|
| Package | 100-pin PQFP | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin TQFP/PQFP - same | 100-pin TQFP/PQFP - same | 100-pin BQFP - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Macro Cells | 128 | 128 - same | 128 - same | 128 - same | 128 - same | 128 - same |
| Propagation Delay (tPD) | 10 ns | 10 ns - same | 10 ns - same | 10 ns - same | 10 ns - same | 10 ns - same |
| RoHS Compliance (N suffix) | Yes (N suffix) | Yes (N suffix implied) | No (leaded) | Yes (N suffix) | No (leaded) | No (leaded) |
| Core Voltage | 5 V | 5 V - same | 5 V - same | 5 V (MAX 7000S) | 5 V (MAX 7000S) | 5 V (MAX 7000B) |
| Family / Series | MAX 7000 | MAX 7000 - same | MAX 7000 - same | MAX 7000S | MAX 7000S | MAX 7000B |
| User I/O Pins | 84 | 84 - same | 84 - same | 84 - same | 84 - same | 84 - same |
| Maximum Frequency | 100 MHz | 100 MHz - same | 100 MHz - same | 100 MHz - same | 100 MHz - same | 100 MHz - same |
主な差別化要因
- 100 MHz maximum operating frequency across full industrial temperature range （vs EPM7128SQC100-15N)
- RoHS-compliant lead-free (N suffix) manufacturing （vs EPM7128SQC100-10)
- Same-family pin-to-pin drop-in compatible with MAX 7000S and MAX 7000B series （vs EPM7128AETC100-10N)
設計ノート
The EPM7128SQC100-10N requires a stable 5V (4.75V to 5.25V) supply on VCCINT pins (9, 28, 48, 69, 88). Place 0.1uF ceramic decoupling capacitors as close as possible to each VCC pin, and add a bulk 10uF tantalum or aluminum electrolytic capacitor at the supply entry. The MultiVolt I/O interface supports 3.3V signaling at the I/O pins while the core operates at 5V - do not mix VCCIO and VCCINT, as the device uses a single 5V rail for both. Avoid powering up with VCC below 4.5V to prevent partial EEPROM configuration corruption.
The 100-pin PQFP package has 0.65 mm pitch gull-wing leads; route all signals on inner PCB layers and use a ground plane on the layer directly beneath the device to minimize EMI. JTAG signals (TCK pin 95, TMS pin 94, TDI pin 93, TDO pin 96) must be routed with 4-8 mil traces and kept short, with TCK having a series 100 ohm termination if the cable exceeds 100 mm. Add 10k ohm pull-ups on TDI, TMS, and TCK to prevent spurious JTAG entry during power-up. Decouple each VCC pin with a separate 0.1uF capacitor - do not share capacitors between adjacent VCC pins.
Do not confuse the EPM7128SQC100-10N with the EPM7128SQC100-7 (faster 7ns variant) or EPM7128SQC100-15N (slower 15ns variant) - the tPD suffix is critical for timing closure. The 'N' suffix indicates RoHS-compliant lead-free manufacturing; the non-N suffix indicates tin-lead finish and is not RoHS compliant. Always use MAX+PLUS II or Quartus Prime software with the correct device family library (max7000) selected; using a generic 'CPLD' library can generate incompatible programming files. The dedicated INPUT/GCLK, INPUT/OE2, INPUT/OE1, and INPUT/CLR pins (52-55) cannot be used as general-purpose I/O - they serve only as global clock, output enable, and clear signals.
コンプライアンス情報
RoHS compliance indicated by 'N' suffix in part number per Altera naming convention. AEC-Q100 not applicable as this is a CPLD not intended for automotive safety-critical applications. REACH compliance assumed per standard Altera product compliance policy.
