EPM7128SQC100-10N vs EPM7128SQC100-7N 比較
詳細な並列比較: EPM7128SQC100-10N メーカー: Altera および EPM7128SQC100-7N メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N Obsolete仕様比較
| パラメータ | EPM7128SQC100-10N | EPM7128SQC100-7N |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.95 | $7.10 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| パッケージ | 100-pin PQFP (BQFP) | 100-pin PQFP (QFP-100) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| 動作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 実装タイプ | Surface Mount | — |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Program Memory Type | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macrocell | — | 32 |
| System Gates | — | 5,000 (max) |
| Maximum User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Counter Speed | — | 175.4 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | — | 5.0 V |
| I/O Standard Support | — | multiVolt (2.5V, 3.3V, 5.0V) |
| RoHS ステータス | — | Compliant (lead-free 'N' suffix) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Security Bit | — | Programmable (one per device) |