EPM7128SQC100-10N vs EPM7128SQC100-7N 비교
다음의 상세 나란히 비교: EPM7128SQC100-10N 제조: Altera 및 EPM7128SQC100-7N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N Obsolete사양 비교
| 파라미터 | EPM7128SQC100-10N | EPM7128SQC100-7N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 활성 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $14.95 | $7.10 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| 패키지 | 100-pin PQFP (BQFP) | 100-pin PQFP (QFP-100) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| 동작 온도 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 실장 유형 | Surface Mount | — |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Program Memory Type | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macrocell | — | 32 |
| System Gates | — | 5,000 (max) |
| Maximum User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Counter Speed | — | 175.4 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | — | 5.0 V |
| I/O Standard Support | — | multiVolt (2.5V, 3.3V, 5.0V) |
| RoHS 상태 | — | Compliant (lead-free 'N' suffix) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Security Bit | — | Programmable (one per device) |