EPM7128SQC100-10N vs EPM7128SQI100-10 比較
詳細な並列比較: EPM7128SQC100-10N メーカー: Altera および EPM7128SQI100-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 Obsolete仕様比較
| パラメータ | EPM7128SQC100-10N | EPM7128SQI100-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.95 | $9.75 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| パッケージ | 100-pin PQFP (BQFP) | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | — |
| 動作温度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount | — |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 (16 macrocells each) |
| Package Type | — | PQFP-100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 125 MHz to 250 MHz |
| Counter Speed | — | Up to 175.4 MHz |
| Operating Voltage (VCC) | — | 5 V |
| Program/Erase Cycles | — | 100 minimum |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Logic Family | — | CMOS |
| I/O Compatibility | — | TTL-compatible, 5V/3.3V multi-voltage |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status not in provided data] |