EPM7128SQC100-7 vs EPM7128SQC100-15 比較
詳細な並列比較: EPM7128SQC100-7 メーカー: Intel および EPM7128SQC100-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 Obsolete
仕様比較
| パラメータ | EPM7128SQC100-7 | EPM7128SQC100-15 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | ラストバイ |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.85 | $8.20 |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Family | MAX 7000S | MAX 7000 |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS, EEPROM-based, non-volatile | — |
| パッケージ | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | Non-RoHS (legacy SnPb package) | Non-compliant (SnPb lead finish - legacy PQFP) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Supply Voltage (VCCINT) | — | 5 V (5% tolerance) |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| MSLレベル | — | 3 (168 hours) |