EPM7128SQC100-7 vs EPM7128SQC100-15 Comparison

Detailed side-by-side comparison of EPM7128SQC100-7 by Intel and EPM7128SQC100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7128SQC100-7 EPM7128SQC100-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Unit Price (USD) — $8.20
Product Type CPLD - Complex Programmable Logic Device —
Family MAX 7000S MAX 7000
Macro Cells 128 —
Usable Gates 2,500 —
User I/Os 84 84
Logic Elements / LABs 4 Logic Array Blocks (LABs) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS, EEPROM-based, non-volatile —
Package 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (Plastic Quad Flat Pack)
Programming Interface JTAG (IEEE Std 1149.1), in-system programmable —
Operating Temperature [DATA_NEEDED: operating temperature range] 0C to +70C (Commercial)
Mounting Type Surface Mount Surface Mount
RoHS Status Non-RoHS (legacy SnPb package) Non-compliant (SnPb lead finish - legacy PQFP)
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 128
Logic Array Blocks (LABs) — 4 (16 macrocells each)
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX value]
Typical Gate Count — 2,500 gates
Supply Voltage (VCCINT) — 5 V (5% tolerance)
Programming Technology — EEPROM (in-system programmable via JTAG)
JTAG Interface — IEEE Std. 1149.1 compliant
MSL Level — 3 (168 hours)

Datasheets & Resources

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