EPM7256AQC208-7 vs EPM7256ATI144-10 比較
詳細な並列比較: EPM7256AQC208-7 メーカー: Altera および EPM7256ATI144-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256AQC208-7 | EPM7256ATI144-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.20 | $10.95 |
| Family | MAX 7000A | MAX 7000A |
| Programmable Type | In System Programmable (ISP), EEPROM-based | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 164 | — |
| Pin-to-Pin Logic Delay (tPD) | 7 ns | — |
| Maximum Counter Frequency | 125 MHz | — |
| Internal Toggle Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V | — |
| I/O Voltage Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| パッケージ | 208-Pin PQFP (28 x 28 mm) | 144-pin TQFP |
| Supplier Device Package | 208-PQFP (28x28) | — |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Speed Grade | -7 | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Non-compliant (legacy Altera marking) |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Maximum Usable Gates | — | 5,000 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 93.5 MHz |
| User I/O Pins | — | 100 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V or 3.3 V |
| Program Memory Type | — | EEPROM (non-volatile) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | EEPROM-based CMOS |