EPM7256AQC208-7 vs EPM7256ATI144-10 Comparison
Detailed side-by-side comparison of EPM7256AQC208-7 by Altera and EPM7256ATI144-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256AQC208-7 | EPM7256ATI144-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $10.95 |
| Family | MAX 7000A | MAX 7000A |
| Programmable Type | In System Programmable (ISP), EEPROM-based | β |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | β |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 164 | β |
| Pin-to-Pin Logic Delay (tPD) | 7 ns | β |
| Maximum Counter Frequency | 125 MHz | β |
| Internal Toggle Frequency | 227.3 MHz | β |
| Supply Voltage - Internal | 3.0 V to 3.6 V | β |
| I/O Voltage Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | β |
| Package | 208-Pin PQFP (28 x 28 mm) | 144-pin TQFP |
| Supplier Device Package | 208-PQFP (28x28) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | -40C to +85C (Industrial) |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Speed Grade | -7 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (legacy Altera marking) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Maximum Usable Gates | β | 5,000 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Frequency (fCNT) | β | 93.5 MHz |
| User I/O Pins | β | 100 |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Voltage (VCCIO) | β | 2.5 V or 3.3 V |
| Program Memory Type | β | EEPROM (non-volatile) |
| In-System Programming | β | Yes (IEEE 1149.1 JTAG) |
| Process Technology | β | EEPROM-based CMOS |