EPM7256SQC208-15 vs EPM7256SQC208-7N 比較
詳細な並列比較: EPM7256SQC208-15 メーカー: Altera および EPM7256SQC208-7N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SQC208-15 | EPM7256SQC208-7N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $3.65 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Series | EPM7256 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 5000 | 5,000 |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Delay (tPD) | 15 ns | 7.5 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| 動作温度範囲 | 0 C to +70 C (Commercial) | — |
| パッケージ | 208-pin PQFP (28x28 mm) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount | Surface Mount |
| Programmable Power Mode | Yes (per-macrocell turbo-bit) | — |
| JTAG (IEEE 1149.1) Boundary-Scan | Yes | — |
| In-System Programmability (ISP) | Yes | — |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| RoHS ステータス | Contains lead / RoHS non-compliant (per third-party listing) | Compliant (N suffix = lead-free) |
| Lead-Free Status | Contains lead | — |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| 動作温度 | — | Commercial (0C to +70C) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Open-Drain Output | — | Optional per I/O pin |