EPM7256SQC208-7 vs EPM7256SQC208-15N 比較
詳細な並列比較: EPM7256SQC208-7 メーカー: Altera および EPM7256SQC208-15N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM7256SQC208-7 | EPM7256SQC208-15N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $0.00 |
| Device Family | MAX 7000S (EPM7256S) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Operating Frequency (fMAX) | 128.2 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| パッケージ | 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) | 208-pin PQFP |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | Commercial (0C to +70C) | — |
| Minimum DC Input Voltage | -0.5 V | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns | — |
| Speed Grade | -7 (7.5 ns) | -15 |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Lead free / RoHS Compliant |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| Logic Levels | 5.0 V CMOS/TTL compatible | — |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| 電源電圧 | — | 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |