EPM9320ALC84-20 vs EPM9320ALI84-10N 比較
詳細な並列比較: EPM9320ALC84-20 メーカー: Altera および EPM9320ALI84-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9320ALC84-20 | EPM9320ALI84-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.50 | $21.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 20 |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| パッケージ | PLCC-84 | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Process Technology | 0.5 µm CMOS EEPROM | CMOS EEPROM |
| 電源電圧 | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| 動作温度 | [DATA_NEEDED: commercial or industrial grade] | -40C to +85C (industrial) |
| 実装タイプ | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Configuration Memory | Non-volatile EEPROM | EEPROM, non-volatile |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| RoHS ステータス | [DATA_NEEDED: per Altera datasheet] | — |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Usable Gates | — | 6,000 to 12,000 |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |