EPM9560RC208-15 vs EPM9560ARC208-10N 比較
詳細な並列比較: EPM9560RC208-15 メーカー: Altera および EPM9560ARC208-10N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RC208-15 | EPM9560ARC208-10N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $0.00 | $27.20 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | 10 ns |
| Counter Speed | 117.6 MHz | — |
| 電源電圧 | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (JTAG ISP) |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Compliant (N suffix) |
| Speed Grade | -15 (15 ns pin-to-pin) | -10 |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 153 |
| Internal Counter Frequency | — | 144.9 MHz |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks (LABs) | — | 20 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSLレベル | — | [DATA_NEEDED: MSL level] |