EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
部品番号: EPM9560RC208-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM9560RC208-15 概要
A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the broader taxonomy, the EPM9560RC208-15 sits in the hierarchy CPLD -> programmable logic device (PLD) -> embedded logic IC -> semiconductor. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated on an advanced CMOS process with EEPROM configuration cells that retain their programmed state without external configuration memory.
Key features include 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 560 macro cells distributed across 12 logic array blocks, and counter speeds up to 117.6 MHz. The EEPROM-based configuration provides non-volatile operation, meaning the device is live at power-up with no boot PROM or configuration controller required - a decisive advantage over SRAM-based FPGAs in glitch-sensitive or fast-boot systems.
The MAX 9000 architecture integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s up to FPGA-class functions, enabling high-density integration of system-level logic. The 208-pin RQFP package provides a high I/O count for bus interfacing, glue logic consolidation, and state-machine implementation.
Typical applications include legacy industrial control backplanes, telecommunications line-card glue logic, test and measurement instrumentation, and replacement of discrete 74-series logic in existing 5 V designs. Because the device is EEPROM-based, it is well suited to applications requiring deterministic power-up behavior.
When designing with this device, note that the MAX 9000 family is a mature 5 V technology; verify availability and consider the MAX 7000 or MAX II families for new designs. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM9560RC208-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC208-15 （同一形状・フットプリント） — 相違点: Package, Speed Grade, Usable Gates, User I/O Pins, Device Type.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC208-14
✅ ドロップイン✓ 在庫あり
$27.9 / 個
データシートを見る →EPM9560RC208-13
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-12
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-10N
✅ ドロップイン✓ 在庫あり
$175 / 個
データシートを見る →EPM9560RC208-10
✅ ドロップイン✓ 在庫あり
$15.4 / 個
データシートを見る →EPM9560ARC208-10N
✅ ドロップイン✓ 在庫あり
$27.2 / 個
データシートを見る →EPM9560ARC208-10
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-15 最大定格＆電気的特性
| Family | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 12,000 gates |
| Macro Cells | 560 macro cells |
| Pin-to-Pin Delay | 15 ns |
| Counter Speed | 117.6 MHz |
| 電源電圧 | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) |
| 実装タイプ | Surface Mount |
| Speed Grade | -15 (15 ns pin-to-pin) |
| Architecture | Third-generation Multiple Array MatriX (MAX) |
EPM9560RC208-15 208-pin rqfp (power quad flat pack) ピン配置ガイド
EPM9560RC208-15 (208-pin rqfp (power quad flat pack) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560RC208-15.
詳細は データシート をご参照ください。
主な用途
EPM9560RC208-15 の用途: 6 件s: Legacy Industrial Control Backplane Glue Logic, Telecommunications Line-Card Glue Logic, Test and Measurement Instrumentation, Replacement of Discrete 74-Series Logic, Bus Interface and Address Decoding, Legacy System Maintenance and Repair.
Legacy Industrial Control Backplane Glue Logic
The EPM9560RC208-15 fits legacy 5 V industrial control backplanes because its 5.0 V supply matches the logic levels of existing 74-series and backplane transceivers, and its 560 macro cells and 12,000 usable gates consolidate dozens of discrete glue-logic packages into one 208-pin RQFP device. Its EEPROM configuration is non-volatile, so the CPLD is live at power-up with no configuration controller, which is critical for deterministic industrial startup. The 15 ns pin-to-pin delay supports bus arbitration and address decoding at backplane speeds. Placed between the backplane bus and local peripherals, it implements chip-select decoding and wait-state generation; the trade-off versus a modern MAX II device is higher static power at 5 V, but no board redesign is required.
おすすめ
Telecommunications Line-Card Glue Logic
The EPM9560RC208-15 suits telecommunications line-card glue logic because its 560 macro cells and 12,000 usable gates implement bus interfacing, clock-domain handshakes, and state machines that would otherwise require multiple PALs and GALs. The MAX 9000 architecture is explicitly designed to integrate devices ranging from PALs and 22V10s up to FPGA-class functions, so a single 208-pin RQFP replaces a board full of small PLDs. Counter speeds up to 117.6 MHz support line-rate state machines, and the 5.0 V supply matches legacy telecom backplane levels. The EEPROM configuration eliminates the boot PROM required by SRAM FPGAs, reducing component count and startup latency on line cards.
おすすめ
Test and Measurement Instrumentation
The EPM9560RC208-15 is used in test and measurement instrumentation where deterministic power-up and 5 V logic compatibility matter. Its 15 ns pin-to-pin delay and 117.6 MHz counter speed support trigger generation, event counting, and digital pattern sequencing. The 208-pin RQFP package provides enough I/O to interface with front-panel controls, display drivers, and measurement front ends on a single device. Because the EEPROM configuration is non-volatile, the instrument boots directly into its programmed state without a configuration PROM, which simplifies the BOM and improves reliability. The trade-off is that the MAX 9000 family is obsolete, so new instrument designs should migrate to MAX II or MAX 10 devices while legacy instruments continue to use the EPM9560RC208-15.
おすすめ
Replacement of Discrete 74-Series Logic
The EPM9560RC208-15 replaces banks of discrete 74-series logic in existing 5 V designs by absorbing counters, shift registers, multiplexers, and decoders into 560 macro cells. This consolidation reduces board area, power, and component count while preserving 5.0 V logic levels, so no level shifters are needed. The 12,000 usable gates and 208-pin RQFP package provide ample I/O for wide buses. In-system programmability through IEEE Std. 1149.1 JTAG allows logic updates after assembly, which is valuable for field fixes. The trade-off versus discrete logic is a higher unit cost and the need for a JTAG programming step, but the reduction in board complexity and improved reliability usually justify the change in legacy 5 V systems.
おすすめ
Bus Interface and Address Decoding
The EPM9560RC208-15 implements bus interface and address decoding because its 208-pin RQFP package provides the high I/O count needed to interface wide address and data buses, while 560 macro cells hold the decode logic and wait-state generators. The 15 ns pin-to-pin delay supports backplane bus cycles, and the 5.0 V supply matches legacy bus transceivers directly. EEPROM configuration means the decoder is active immediately at power-up, avoiding the configuration delay of SRAM-based devices. Placed between the host bus and peripheral chips, it generates chip selects and handshake signals; the trade-off is that the 15 ns grade limits maximum bus frequency compared with the 10 ns grade, so timing-critical buses should use the EPM9560RC208-10 instead.
おすすめ
Legacy System Maintenance and Repair
The EPM9560RC208-15 is critical for legacy system maintenance and repair because it is the exact speed grade used in many existing 5 V designs, and substituting a different grade can require requalification. Its 208-pin RQFP footprint matches the original land pattern, so field replacement needs no board rework. The EEPROM configuration retains the programmed logic without a battery or configuration PROM, simplifying spares management. Because the device is obsolete, maintenance organizations stock remaining distributor inventory and qualify pin-compatible speed-grade alternatives such as the EPM9560RC208-10 as second sources. The trade-off is limited long-term availability, so repair depots should secure stock or plan a board redesign before inventory is exhausted.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC208-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC208-14 | EPM9560RC208-10 | EPM9560ARC208-10 |
|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay | 15 ns | 14 ns | 10 ns | 10 ns |
| Macro Cells | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| JTAG ISP | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) | Yes (IEEE Std. 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Non-volatile EEPROM configuration （vs SRAM-based FPGAs)
- Pin-compatible speed-grade upgrade path （vs EPM9560RC208-10)
- High logic density in a single 5 V device （vs EPM9320RC208-15)
設計ノート
Decouple every VCC pin of the EPM9560RC208-15 with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus at least one 10 uF bulk capacitor per power plane. The MAX 9000 family operates from a 5.0 V supply; keep the supply within the datasheet tolerance to avoid EEPROM configuration corruption during in-system programming. Estimated: at 5.0 V and typical MAX 9000 quiescent current, a single 0.1 uF per pin plus 10 uF bulk is sufficient for the 208-pin RQFP package, but confirm the exact ICC figure in the Altera MAX 9000 datasheet before finalizing the power budget.
Route the IEEE Std. 1149.1 JTAG signals (TCK, TMS, TDI, TDO) as short, matched traces with a solid ground return, and keep TCK away from high-speed I/O to prevent accidental state-machine transitions during programming. Place the JTAG header close to the device and add series termination if trace length exceeds a few centimeters. Because the EPM9560RC208-15 is EEPROM-based, the JTAG chain must be stable during in-system programming; a noisy TCK can corrupt configuration. Follow the Altera MAX 9000 device family datasheet recommendations for the JTAG chain topology.
Do not assume the EPM9560RC208-15 is available long-term: Altera issued a product discontinuance notice for selected MAX 9000 ordering codes, discontinuing the EPM9560 in the 208-pin CQFP and substituting RQFP alternatives. For new designs, migrate to the MAX 7000 or MAX II families. For existing designs, qualify a pin-compatible speed-grade alternative such as the EPM9560RC208-10 before inventory runs out. Also verify that the 208-pin RQFP land pattern matches the original CQFP-to-RQFP substitution, since Altera states the RQFP is form, fit, and functionally equivalent to the CQFP.
コンプライアンス情報
No compliance data was present in the verified web data for the EPM9560RC208-15. The lead-free 'N' suffix variants (EPM9560RC208-10N, EPM9560ARC208-10N) exist in the same family, but RoHS/REACH status for this exact ordering code must be confirmed with the manufacturer or distributor.