EPM9560RC208-15 vs EPM9560ARC208-10N 비교
다음의 상세 나란히 비교: EPM9560RC208-15 제조: Altera 및 EPM9560ARC208-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9560RC208-15 | EPM9560ARC208-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $0.00 | $27.20 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | 10 ns |
| Counter Speed | 117.6 MHz | — |
| 공급 전압 | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (JTAG ISP) |
| 패키지 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | Compliant (N suffix) |
| Speed Grade | -15 (15 ns pin-to-pin) | -10 |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 153 |
| Internal Counter Frequency | — | 144.9 MHz |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks (LABs) | — | 20 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |