EPM9560RC208-4 vs EPM9560RC208-15 比較
詳細な並列比較: EPM9560RC208-4 メーカー: Altera および EPM9560RC208-15 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM9560RC208-4 | EPM9560RC208-15 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $62.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum Operating Frequency | 118.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 4 ns | — |
| Speed Grade | -4 | -15 (15 ns pin-to-pin) |
| Supply Voltage (VCC) | 5 V | — |
| パッケージ | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 96 (approx., 208-pin RQFP) | — |
| Dedicated Inputs | 16 | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| MultiVolt I/O | 5.0 V / 3.3 V / 2.5 V | — |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| 電源電圧 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| 実装タイプ | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |