EPM9560RC304-15 vs EPM9560RC304-15C 比較
詳細な並列比較: EPM9560RC304-15 メーカー: Altera および EPM9560RC304-15C メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C Obsolete仕様比較
| パラメータ | EPM9560RC304-15 | EPM9560RC304-15C |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.40 | $24.50 |
| Device Family | MAX 9000 | — |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | Multiple Array MatriX (MAX), 3rd generation |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 212 (maximum) | — |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) | — |
| ピン数 | 304 | — |
| パッケージ | 304-pin RQFP (Plastic Quad Flat Pack) | 304-pin RQFP |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standard | 5.0 V TTL / PCI-compliant | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE 1149.1 JTAG) |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Technology Node | High-performance CMOS, EEPROM process | — |
| 動作温度 | [DATA_NEEDED: industrial/commercial temperature grade] | 0 C to +70 C (Commercial) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: lead-free / RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| 電源電圧 | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Program/Erase Endurance | — | 100 cycles minimum |