LTC2309IF vs LTC2313HTS8-14 比較
詳細な並列比較: LTC2309IF メーカー: Analog Devices および LTC2313HTS8-14 メーカー: Analog Devices。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ 生産中仕様比較
| パラメータ | LTC2309IF | LTC2313HTS8-14 |
|---|---|---|
| ブランド | Analog Devices | Analog Devices |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.50 | $4.10 |
| 分解能 | 12 bit | 14 bits |
| Number of Input Channels | 8 single-ended / 4 differential | 1 (single-ended/differential) |
| Architecture | SAR (Successive Approximation Register) | SAR (Successive Approximation Register) |
| Conversion Time | 1.3 us per channel (typical) | — |
| Throughput Rate | up to 500 ksps (datasheet-dependent) | — |
| Supply Voltage (VDD) | 5 V single supply | — |
| 電源電流 | 300 uA at 1 ksps (typical) | 5 mA at 2.5 Msps |
| Digital Interface | I2C-compatible, standard / fast / high-speed modes | — |
| I2C Address Selection | 2 pins (AD0, AD1) - up to 4 devices on one bus | — |
| Internal Reference | 2.5 V, 10 ppm/C typical drift | 2.5 V nominal, 20 ppm/°C max drift |
| External Reference Input (REFIN) | Yes, supports ratiometric operation | — |
| Sample-and-Hold | Fully differential, common-mode noise rejection | — |
| Analog Input Range | 0 V to VDD (unipolar); +/-VREF differential | — |
| パッケージ | 20-TSSOP (FE) | TSOT-23-8 (HTS8) |
| Operating Temperature Range (I grade) | -40 C to +85 C | — |
| シャットダウン電流 | Nap / I2C power-down supported | — |
| RoHS ステータス | Compliant (PBF suffix) | Compliant |
| Sample Rate | — | 2.5 Msps |
| 電源電圧 | — | 3 V to 5 V (single supply, 5 V typical) |
| Input Type | — | Pseudo-differential (IN+, IN-) |
| Serial Interface | — | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| 動作温度範囲 | — | -40 °C to +125 °C (H-grade) |
| 実装タイプ | — | Surface Mount |
| MSLレベル | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |