LTC2309IF vs LTC2313HTS8-14 비교
다음의 상세 나란히 비교: LTC2309IF 제조: Analog Devices 및 LTC2313HTS8-14 제조: Analog Devices. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Analog Devices
LTC2313HTS8-14 - 14-bit 2.5Msps SAR ADC in TSOT-23-8 | Analog Devices
LTC2313HTS8-14 ✓ 활성사양 비교
| 파라미터 | LTC2309IF | LTC2313HTS8-14 |
|---|---|---|
| 브랜드 | Analog Devices | Analog Devices |
| 카테고리 | ADC/DAC | ADC/DAC |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.50 | $4.10 |
| 분해능 | 12 bit | 14 bits |
| Number of Input Channels | 8 single-ended / 4 differential | 1 (single-ended/differential) |
| Architecture | SAR (Successive Approximation Register) | SAR (Successive Approximation Register) |
| Conversion Time | 1.3 us per channel (typical) | — |
| Throughput Rate | up to 500 ksps (datasheet-dependent) | — |
| Supply Voltage (VDD) | 5 V single supply | — |
| 공급 전류 | 300 uA at 1 ksps (typical) | 5 mA at 2.5 Msps |
| Digital Interface | I2C-compatible, standard / fast / high-speed modes | — |
| I2C Address Selection | 2 pins (AD0, AD1) - up to 4 devices on one bus | — |
| Internal Reference | 2.5 V, 10 ppm/C typical drift | 2.5 V nominal, 20 ppm/°C max drift |
| External Reference Input (REFIN) | Yes, supports ratiometric operation | — |
| Sample-and-Hold | Fully differential, common-mode noise rejection | — |
| Analog Input Range | 0 V to VDD (unipolar); +/-VREF differential | — |
| 패키지 | 20-TSSOP (FE) | TSOT-23-8 (HTS8) |
| Operating Temperature Range (I grade) | -40 C to +85 C | — |
| 셧다운 전류 | Nap / I2C power-down supported | — |
| RoHS 상태 | Compliant (PBF suffix) | Compliant |
| Sample Rate | — | 2.5 Msps |
| 공급 전압 | — | 3 V to 5 V (single supply, 5 V typical) |
| Input Type | — | Pseudo-differential (IN+, IN-) |
| Serial Interface | — | SPI-compatible SCK/SDO/SDI/CSF, supports 1.8 V/2.5 V/3 V/5 V logic |
| No-Missing-Codes Performance | — | 14 bits guaranteed |
| Latency | — | 0 conversion latency |
| 동작 온도 범위 | — | -40 °C to +125 °C (H-grade) |
| 실장 유형 | — | Surface Mount |
| MSL 레벨 | — | 1 (per JEDEC J-STD-020) |
| Conversion Cycles | — | 16 SCK per conversion (14-bit plus 2 dummy bits) |