MC9S12DG256CMPV vs MC9S12DG256CCPV 比較
詳細な並列比較: MC9S12DG256CMPV メーカー: NXP Semiconductors および MC9S12DG256CCPV メーカー: NXP Semiconductors。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
NXP Semiconductors
MC9S12DG256CMPV - 16-bit HCS12 MCU 256KB Flash 112-LQFP | NXP
MC9S12DG256CMPV ✓ 生産中NXP Semiconductors
MC9S12DG256CCPV - HCS12 16-bit MCU, 256KB Flash, 112-LQFP | NXP
MC9S12DG256CCPV Nrnd仕様比較
| パラメータ | MC9S12DG256CMPV | MC9S12DG256CCPV |
|---|---|---|
| ブランド | NXP Semiconductors | NXP Semiconductors |
| カテゴリ | Microcontrollers | Microcontrollers |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $11.90 | $18.20 |
| Core | HCS12 CPU12 (CISC, 16-bit, upward-compatible with HC11) | HCS12 (16-bit CISC) |
| Maximum CPU Clock | 25 MHz (50 MHz effective instruction throughput via look-ahead fetch) | — |
| Program Memory (Flash) | 256 KB (256K x 8) | 256 KB (256K x 8) |
| RAM | 12 KB | — |
| EEPROM | 4 KB | — |
| Operating Voltage | 2.5 V / 5 V (single supply with on-chip regulator) | — |
| I/O Voltage | 5 V tolerant | — |
| ADC | 10-bit, 8 channels | 8-channel, 10-bit |
| CAN Modules (MSCAN) | 1 x MSCAN 2.0A/B-compatible | — |
| SCI / SPI | 2 x SCI, 1 x SPI | — |
| Timers | Enhanced Capture Timer (ECT), 8 x PWM, 1 x RTI | Enhanced Capture Timer (ECT) + watchdog |
| BDLC (J1850) | 1 module (VPW) | — |
| パッケージ | 112-LQFP (20 x 20 mm, 0.65 mm pitch) | — |
| ピン数 | 112 | — |
| 動作温度 | -40 C to +85 C (automotive AEC-Q100) | — |
| AEC-Q100 Qualification | Qualified (automotive grade) | — |
| 実装タイプ | Surface Mount (gull-wing) | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS status - not present in verified snippet] | Compliant |
| Maximum CPU/Bus Frequency | — | 25 MHz |
| RAM Size | — | 12 KB |
| EEPROM Size | — | 4 KB |
| Number of I/O Lines | — | 91 |
| Supply Voltage Range | — | 2.97 V to 5.5 V (single 5 V supply) |
| 動作温度範囲 | — | -40 °C to +85 °C (industrial) |
| パッケージ / ケース | — | 112-LQFP (20 x 20 mm) |
| PWM Channels | — | 8 channels |
| Communication Interfaces | — | 2 x SCI, 2 x SPI, I2C, CAN 2.0 |
| On-chip Debug | — | Background Debug Mode (BDM) |
| MSLレベル | — | 3 (168 hours, JEDEC J-STD-020) |