RTAX1000SL-1CGS624B vs RTAX1000SL-1CGS624V 比較

詳細な並列比較: RTAX1000SL-1CGS624B メーカー: Microchip Technology および RTAX1000SL-1CGS624V メーカー: Microchip Technology。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

Microchip Technology
RTAX1000SL-1CGS624B RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip

RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip

RTAX1000SL-1CGS624B ✓ 生産中
Microchip Technology
RTAX1000SL-1CGS624V RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V ✓ 生産中

仕様比較

パラメータ RTAX1000SL-1CGS624B RTAX1000SL-1CGS624V
ブランド Microchip Technology Microchip Technology
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 有効 有効
在庫状況 In Stock In Stock
単価(USD) $3,200.00 $1.00
Logic Density 1,000,000 equivalent system gates —
ASIC Gates 125,000 additional ASIC gates —
Configurable Logic Blocks (CLBs) 12096 —
Family RTAX-S/SL Radiation-Tolerant FPGA —
Series RTAX1000SL —
Speed Grade -1 -1 (standard)
Technology Digital CMOS —
Programming Technology Anti-fuse (one-time programmable, live at power-up) —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
パッケージ 624-ball Ceramic CGA (CGS624) —
実装タイプ Surface Mount Surface Mount
Radiation Tolerance Radiation-tolerant (space flight qualified) Radiation-tolerant (space-flight qualified family)
Qualification DLA SMD 5962-0422006QUA per MIL-PRF-38535 —
動作温度 [DATA_NEEDED: operating temperature range] -55C to +125C
電源電圧 [DATA_NEEDED: core/IO supply voltage] [DATA_NEEDED: core/IO supply voltage]
Maximum User I/O [DATA_NEEDED: maximum user I/O count] —
RoHS ステータス [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Architecture Base Derived from Microsemi commercial Axcelerator family —
System Gates — 1,000,000 (1.00E6)
Logic Cells / Logic Blocks — 12096
Logic Family — Digital CMOS
Programmable Technology — Antifuse (one-time programmable)
Package Type — CGA-624 (ceramic column grid array)
ピン数 — 624
SEU Immunity — SEU-hardened registers; SEU rate < 10-10 errors/bit-day
Configuration — Live at power-up, single chip, no external boot PROM
Clocking — Segmentable clock resources
Routing Features — Chip-wide highway routing, carry logic

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