RTAX1000SL-1CGS624B vs RTAX1000SL-1CGS624V 비교

다음의 상세 나란히 비교: RTAX1000SL-1CGS624B 제조: Microchip Technology 및 RTAX1000SL-1CGS624V 제조: Microchip Technology. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

Microchip Technology
RTAX1000SL-1CGS624B RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip

RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip

RTAX1000SL-1CGS624B ✓ 활성
Microchip Technology
RTAX1000SL-1CGS624V RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip

RTAX1000SL-1CGS624V ✓ 활성

사양 비교

파라미터 RTAX1000SL-1CGS624B RTAX1000SL-1CGS624V
브랜드 Microchip Technology Microchip Technology
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 활성
재고 상태 In Stock In Stock
단가 (USD) $3,200.00 $1.00
Logic Density 1,000,000 equivalent system gates —
ASIC Gates 125,000 additional ASIC gates —
Configurable Logic Blocks (CLBs) 12096 —
Family RTAX-S/SL Radiation-Tolerant FPGA —
Series RTAX1000SL —
Speed Grade -1 -1 (standard)
Technology Digital CMOS —
Programming Technology Anti-fuse (one-time programmable, live at power-up) —
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
패키지 624-ball Ceramic CGA (CGS624) —
실장 유형 Surface Mount Surface Mount
Radiation Tolerance Radiation-tolerant (space flight qualified) Radiation-tolerant (space-flight qualified family)
Qualification DLA SMD 5962-0422006QUA per MIL-PRF-38535 —
동작 온도 [DATA_NEEDED: operating temperature range] -55C to +125C
공급 전압 [DATA_NEEDED: core/IO supply voltage] [DATA_NEEDED: core/IO supply voltage]
Maximum User I/O [DATA_NEEDED: maximum user I/O count] —
RoHS 상태 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Architecture Base Derived from Microsemi commercial Axcelerator family —
System Gates — 1,000,000 (1.00E6)
Logic Cells / Logic Blocks — 12096
Logic Family — Digital CMOS
Programmable Technology — Antifuse (one-time programmable)
Package Type — CGA-624 (ceramic column grid array)
핀 수 — 624
SEU Immunity — SEU-hardened registers; SEU rate < 10-10 errors/bit-day
Configuration — Live at power-up, single chip, no external boot PROM
Clocking — Segmentable clock resources
Routing Features — Chip-wide highway routing, carry logic

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