SI5345A-D-GM vs SI5345B-D-GM 比較
詳細な並列比較: SI5345A-D-GM メーカー: Skyworks Solutions および SI5345B-D-GM メーカー: Skyworks Solutions。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Skyworks Solutions
SI5345A-D-GM - 10-Output Jitter Attenuator, <1028 MHz | Skyworks
SI5345A-D-GM ✓ 生産中仕様比較
| パラメータ | SI5345A-D-GM | SI5345B-D-GM |
|---|---|---|
| ブランド | Skyworks Solutions | Skyworks Solutions |
| カテゴリ | Clock & Timing | Clock & Timing |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $27.50 | $8.55 |
| Product Type | 10-Channel Any-Frequency Any-Output Jitter Attenuator / Clock Multiplier | — |
| Series | Si5345 (Si5345A/B/C/D variants) | — |
| 出力数 | 10 | 10 |
| Differential Input Frequency Range | 8 kHz to 750 MHz | — |
| LVCMOS Input Frequency Range | 8 kHz to 250 MHz | — |
| Differential Output Frequency Range | 100 Hz to 1028 MHz | — |
| Output RMS Jitter | 90 fs typical (12 kHz to 20 MHz) | — |
| External Crystal Reference | 25 to 54 MHz (XA/XB pins) | — |
| Jitter Attenuation Bandwidth | Digitally programmable | Digitally programmable |
| Architecture | DSPLL with digital holdover | — |
| Configuration Interface | I2C / SPI (ClockBuilder Pro software) | — |
| パッケージ | 64-VFQFN Exposed Pad (QFN-64 EP, 9x9 mm) | 64-pin QFN Exposed Pad (9x9 mm) |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度範囲 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 電源電圧 | 1.8 V / 2.5 V / 3.3 V core and I/O (per register config) | 1.8 V / 3.3 V (core / IO) |
| RoHS ステータス | Compliant | Compliant |
| Lead-Free / Halogen-Free | Lead-free per Skyworks product page | — |
| 機能 | — | 10-channel any-frequency jitter attenuator / clock multiplier |
| Output Frequency Range | — | 0.001 MHz to 350 MHz |
| Phase Jitter (RMS, typical) | — | 0.09 ps |
| Reference Input Frequency Range | — | [DATA_NEEDED: reference input frequency range] |
| Output Logic Formats | — | LVCMOS, LVDS, LVPECL, HCSL, CML |
| Control Interface | — | I2C / SPI (serial) |
| On-chip NVM | — | Yes (in-circuit programmable, powers up configured) |
| Technology | — | DSPLL (4th gen) + MultiSynth fractional dividers |
| MSLレベル | — | [DATA_NEEDED: MSL level] |