10AS032H2F35I2LG - Arria 10 SX SoC FPGA, 320K LE | Intel/Altera
部品番号: 10AS032H2F35I2LG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 100 | $1565 | $156,500.00 |
| 250 | $1430 | $357,500.00 |
| 500 | $1295 | $647,500.00 |
10AS032H2F35I2LG 概要
An SoC FPGA (System-on-Chip Field-Programmable Gate Array) is a hybrid device that combines a hard ASIC processor subsystem with reconfigurable FPGA fabric on a single die. Within the broader taxonomy it sits as a programmable logic device -> FPGA -> SoC FPGA -> embedded computing platform, allowing deterministic hardware acceleration alongside a full operating-system-capable application processor.
Key features include 320K logic elements, 1.5 GHz core fabric performance, integrated dual ARM Cortex-A9 cores with CoreSight, industrial temperature grade, and the high-pin-count FCBGA-1152 package that supports high-speed serial transceivers and abundant external memory interfaces. The part is part of Altera's Arria 10 SX mid-range SoC FPGA portfolio targeting compute-intensive embedded designs.
The Arria 10 architecture uses TSMC's 20 nm process with a heterogeneous fabric combining adaptive logic modules (ALMs), M20K on-chip SRAM blocks, variable-precision DSP blocks. The hard processor subsystem removes the latency and area penalty of soft CPU cores and includes caches, ECC, and coherent interconnect to FPGA fabric, simplifying Linux/RTOS deployment alongside custom accelerators.
Typical applications include industrial machine vision, software-defined radio, motor control and industrial drives, military/aerospace signal processing, and high-performance embedded computing platforms. The dual 1.5 GHz Cortex-A9 cores also suit low-latency deterministic control loops paired with FPGA-side sensor fusion.
When designing with this device, ensure your PCB accommodates the 35x35 mm BGA with appropriate microvia stack-up and matched-length routing for DDR3/4 and high-speed serial links. Thermal management must consider both ARM core and FPGA fabric power; Intel/Altera's PowerPlay early power estimator is the recommended starting point.
This page synthesizes distributor pricing, drop-in OPN alternatives, and practical design guidance for the 10AS032H2F35I2LG - information not consolidated on any single distributor or manufacturer page.
ドロップイン代替品: 10AS032H2F35I2LG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AS032H2F35I2LG （同一形状・フットプリント） — 相違点: Package, Process Technology, Transceivers, DSP Blocks, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
10AS032H2F35I1HG
✅ ドロップイン✓ 在庫あり
$2890 / 個
データシートを見る →10AS032H2F35E2SG
✅ ドロップイン✓ 在庫あり
$1325 / 個
データシートを見る →10AS032H2F35E2LG
✅ ドロップイン✓ 在庫あり
$2310 / 個
データシートを見る →10AS032H2F35E1HG
✅ ドロップイン✓ 在庫あり
$1293 / 個
データシートを見る →10AS032H1F35I1HG
✅ ドロップイン✓ 在庫あり
$2265 / 個
データシートを見る →10AS032H1F35E1HG
✅ ドロップイン✓ 在庫あり
$2540 / 個
データシートを見る →10AS032H2F35I2LG 最大定格＆電気的特性
| Family | Arria 10 SX |
| Device Variant | 10AS032 (320K Logic Elements) |
| Architecture | SoC FPGA (FPGA + Hard Processor System) |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 320 K |
| Maximum Logic Performance | 1.5 GHz |
| パッケージ | 1152-FBGA, FC (Flip-Chip), 35x35 mm (F35) |
| 実装タイプ | Surface Mount |
| Operating Temperature Grade | Industrial (I2 suffix) |
| RoHS ステータス | Compliant |
| Lead Free | Yes |
| Number of Terminals | 1152 (Ball) |
| Terminal Form | Ball |
| Package Code | BGA (FCBGA) |
10AS032H2F35I2LG bga (fcbga) ピン配置ガイド
10AS032H2F35I2LG (bga (fcbga) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: 10AS032H2F35I2LG.
詳細は データシート をご参照ください。
主な用途
10AS032H2F35I2LG の用途: 7 件s: Industrial Machine Vision, Software Defined Radio (SDR), Motor Control and Industrial Drives, High-Performance Embedded Computing, Medical Imaging and Diagnostics, Military and Aerospace Signal Processing, Broadcast and Video Processing.
Industrial Machine Vision
The 10AS032H2F35I2LG is well-suited for industrial machine vision systems where the dual ARM Cortex-A9 cores host Linux image-processing pipelines while the 320K logic elements accelerate pixel-level operations such as convolution, feature extraction, and object detection. The 1152-ball F35 package supplies abundant I/O for multiple MIPI CSI-2 or GigE Vision camera interfaces, and the industrial temperature grade supports factory-floor deployment without thermal screening. Per Arria 10 SX datasheet typical applications, machine vision is a flagship use case.
おすすめ
Software Defined Radio (SDR)
The 10AS032H2F35I2LG delivers the logic density and DSP blocks required to implement wideband SDR baseband processing in the FPGA fabric while the dual Cortex-A9 cores manage the network stack and control plane. The F35 BGA exposes the high-speed serial transceivers needed for ADC/DAC interface, and the 1.5 GHz fabric performance supports LTE-class throughput. Per Altera Arria 10 SX application notes, SDR is a primary vertical for the SoC FPGA family.
おすすめ
Motor Control and Industrial Drives
The 10AS032H2F35I2LG combines deterministic ARM Cortex-A9 cores for control-loop execution with FPGA-side high-resolution PWM generation and encoder decoding for multi-axis servo drives. The F35 1152-ball package provides ample I/O for resolver, encoder, and gate-driver interfaces across multiple axes. The industrial temperature grade and 20 nm Arria 10 process deliver predictable performance in factory automation cells.
おすすめ
High-Performance Embedded Computing
The 10AS032H2F35I2LG enables embedded computing platforms that demand OS-capable application processors and FPGA-side compute acceleration on a single chip. The dual 1.5 GHz Cortex-A9 cores run Linux/RTOS while 320K logic elements accelerate signal processing, encryption, or compression. The F35 1152-ball FCBGA exposes PCIe and high-speed serial lanes for backplane or compute fabric integration, making this OPN suitable for radar, sonar, and tactical systems.
おすすめ
Medical Imaging and Diagnostics
The 10AS032H2F35I2LG supports medical imaging modalities (ultrasound beamforming, endoscopy video processing, patient monitoring DSP) by offloading pixel-level pipelines to its 320K logic elements while the ARM cores manage UI, connectivity, and patient data handling. Per Arria 10 SX family documentation, the SoC's medical-grade reliability plus deterministic real-time response suits diagnostic equipment. Industrial temperature grade supports clinical equipment enclosures.
おすすめ
Military and Aerospace Signal Processing
The 10AS032H2F35I2LG supports defense signal-processing applications where FPGA-accelerated FFT, channelization, and crypto must coexist with a hardened ARM subsystem for control and I/O management. The Arria 10 SX 20 nm process delivers predictable performance for radar, electronic warfare, and secure-communications designs. Industrial-grade screening plus ruggedization options extend deployment to airborne and naval platforms. Per Altera defense collateral, the SoC family is widely used in mission computing.
おすすめ
Broadcast and Video Processing
The 10AS032H2F35I2LG combines the ARM subsystem for stream control and the FPGA fabric for video codec acceleration, frame-rate conversion, and overlay composition. The 1152-ball F35 BGA delivers sufficient I/O for multi-stream SDI, HDMI, or DisplayPort interfaces. Per Arria 10 SX broadcast application notes, this OPN class is used in professional video switchers, encoders, and contribution encoders.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AS032H2F35I2LG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AS032H2F35I1HG | 10AS032H2F35E2SG | 10AS032H2F35E2LG | 10AS032H2F35E1HG | 10AS032H1F35I1HG | 10AS032H1F35E1HG |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1152-FBGA, FC (35x35 mm F35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 320 K | 320 K | 320 K | 320 K | 320 K | 320 K | 320 K |
| Processor Core | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore |
| Temperature Grade Suffix | I2 (Industrial) | I1 (Industrial) | E2 (Extended) | E2 (Extended) | E1 (Extended) | I1 (Industrial) | E1 (Extended) |
| Speed Grade | H2 | H2 | H2 | H2 | H2 | H1 (-1 bin) | H1 (-1 bin) |
| RoHS Compliance | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- Hard ARM Cortex-A9 dual-core SoC subsystem on die （vs Pure FPGA 10AX-series)
- 320K logic elements in the 10AS tier （vs 10AS016 or 10AS022)
- I2 industrial temperature grade with H2 speed bin （vs 10AS032H1F35I1HG (H1 speed, I1 grade))
設計ノート
The F35 1152-FBGA flip-chip BGA requires a high-density PCB stack-up with microvias (laser-drilled stacked or staggered). Use a 1.0-1.5 mm BGA pitch escape routing strategy with at least 6-8 metal layers. Matched-length routing for DDR3/4 channels, PCIe, and high-speed serial transceivers must follow the Intel/Altera pin-out files exactly. A signal-integrity-aware stackup with controlled-impedance reference planes is mandatory for transceiver performance above 6 Gbps.
Estimated: at typical Arria 10 SX utilization (50% logic, dual ARM Cortex-A9 cores active), power can reach 15-25 W. The 35x35 mm F35 FCBGA exposed-die package requires a heatsink with thermal interface material and adequate airflow (typically 200-400 LFM). Use Intel/Altera's PowerPlay early power estimator to model worst-case junction temperature. Without cooling, junction temperature can exceed the 100 C industrial limit at high ambient.
Do not use a non-Intel/Altera pin-out file with third-party BGA reballing services - the F35 ball map is device-specific and HPS ball assignments must match exactly or the hard processor subsystem will not boot. Verify each lot against the official Intel/Altera OPN, as some lots include revised bond-out revisions (Rev A vs Rev B silicon). Always generate the Quartus Prime pin assignment report from the project's compiled design for production documentation.
The Arria 10 SX SoC requires multiple power rails: 0.85V/0.95V core, 1.1V/1.2V transceiver, 1.5V/1.8V/3.3V I/O, plus HPS-specific rails for the ARM cores. Use Intel/Altera's recommended power sequencer IC (e.g., LTC2978 or ISLUSPLUS family) to enforce safe power-up/power-down sequencing. Failure to sequence correctly can damage the die or cause HPS lockup.
コンプライアンス情報
RoHS compliance confirmed via Altera product page ordering information section. AEC-Q100 not applicable - this is a non-automotive SoC FPGA. Reach and halogen-free status not stated in verified web data.
