10CL016YM164C6G - Cyclone 10 LP FPGA 16K LE 164-MBGA | Intel
部品番号: 10CL016YM164C6G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.4 | $284.00 |
| 100 | $24.15 | $2,415.00 |
| 500 | $20.95 | $10,475.00 |
| 1,000 | $18.4 | $18,400.00 |
10CL016YM164C6G 概要
A Field-Programmable Gate Array (FPGA) is a reprogrammable semiconductor that combines configurable logic blocks (CLBs), programmable interconnect, and on-chip memory into a single device, allowing engineers to implement custom digital circuits, state machines, and parallel processing pipelines in hardware. FPGAs sit within the broader programmable logic hierarchy (PLD -> CPLD -> FPGA) and are widely used for I/O expansion, custom protocol bridging, and hardware acceleration in embedded systems.
The 10CL016YM164C6G provides up to 87 user I/O pins, 56 embedded 18x18 multipliers, 2 4 PLLs, and 4 Mb of configuration memory (typical). It supports common interfaces such as LVDS, DDR3, and LPDDR2 through the hardened memory controller, and integrates a JTAG interface for boundary-scan and in-system programming via the Quartus Prime design suite.
Architecturally, Cyclone 10 LP devices use a low-power 60-nm process technology with adaptive logic modules (ALMs), variable-precision DSP blocks, and a configurable 8-lane transceiver at speeds up to 250 MHz. The device's energy-efficient logic fabric makes it the preferred choice for portable and thermally constrained products.
Typical applications include industrial motor control, video bridging, sensor aggregation, low-cost protocol bridging (I2C/SPI/UART to Ethernet), and entry-level software-defined radio front ends. The 164-pin MBGA package provides a compact 8 x 8 mm footprint suited for space-constrained designs.
When designing with this part, plan for a 1.2 V core supply and a separate 2.5 V/3.3 V bank supply. Use the Quartus Prime PowerPlay early power estimator to characterize dynamic power before final layout.
This page consolidates verified distributor pricing, same-package drop-in alternatives from the Cyclone 10 LP family, and application guidance not found in the standalone datasheet.
ドロップイン代替品: 10CL016YM164C6G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10CL016YM164C6G （同一形状・フットプリント） — 相違点: Package, MSL Level, Core Voltage, Embedded Memory, PLLs.
クイック比較ツール — 並列比較する代替部品を選択:
10CL016YM164A7G
✅ ドロップイン✓ 在庫あり
$16.75 / 個
データシートを見る →10CL016YM164I7G
✅ ドロップイン✓ 在庫あり
$12.95 / 個
データシートを見る →10CL016YM164C8G
✅ ドロップイン✓ 在庫あり
$17.1 / 個
データシートを見る →10CL010YM164C6G
✅ ドロップイン✓ 在庫あり
$11.4 / 個
データシートを見る →10CL010YM164C8G
✅ ドロップイン✓ 在庫あり
$12.1 / 個
データシートを見る →10CL010YM164I7G
✅ ドロップイン✓ 在庫あり
$9.45 / 個
データシートを見る →10CL016YM164C6G 最大定格＆電気的特性
| Family | Cyclone 10 LP |
| Logic Elements (LE) | 15,408 |
| Embedded Memory | 516,096 bits |
| User I/O | 87 |
| DSP Blocks (18x18 Multipliers) | 56 |
| PLLs | 2 4 |
| Core Voltage | 1.2 V (1.15 V min, 1.25 V max) |
| パッケージ | 164-MBGA (TFBGA, 8 x 8 mm) |
| JEDEC Package Code | S-PBGA-B164 |
| Temperature Grade | Commercial (0C to 85C) |
| Process Node | 60 nm |
| Configuration Memory | 4 Mb |
| 動作温度 | 0C to 85C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
10CL016YM164C6G ピン構成
| ピン A1 | — User I/O pin (bank 1A) |
| ピン A2 | — User I/O pin (bank 1A) |
| ピン A3 | — User I/O pin (bank 1A) |
| ピン A4 | — VCCIO bank 1A |
| ピン A5 | — User I/O pin (bank 1B) |
| ピン A6 | — User I/O pin (bank 1B) |
| ピン A7 | — User I/O pin (bank 1B) |
| ピン A8 | — User I/O pin (bank 1B) |
| ピン A9 | — User I/O pin (bank 1B) |
| ピン A10 | — User I/O pin (bank 1B) |
| ピン A11 | — User I/O pin (bank 1B) |
| ピン A12 | — User I/O pin (bank 1B) |
| ピン B1 | — User I/O pin (bank 1A) |
| ピン B2 | — GND |
| ピン B3 | — User I/O pin (bank 1A) |
| ピン B4 | — User I/O pin (bank 1A) |
| ピン B5 | — User I/O pin (bank 1B) |
| ピン B6 | — User I/O pin (bank 1B) |
| ピン B7 | — VCCIO bank 1B |
| ピン B8 | — User I/O pin (bank 1B) |
| ピン B9 | — User I/O pin (bank 1B) |
| ピン B10 | — User I/O pin (bank 1B) |
| ピン B11 | — User I/O pin (bank 1B) |
| ピン B12 | — User I/O pin (bank 1B) |
主な用途
10CL016YM164C6G の用途: 6 件s: Industrial Motor Control, Video Bridging and Image Aggregation, Low-Cost Protocol Bridging, Sensor Aggregation Hubs, Entry-Level Software-Defined Radio, Automotive Infotainment Auxiliary Logic.
Industrial Motor Control
The 10CL016YM164C6G fits industrial motor control because its 56 dedicated 18-bit DSP multipliers implement field-oriented control (FOC) loops and PWM generation, while the 15,408 logic elements encode the state machine, encoder interface (QEP), and protection logic. With 87 user I/O pins, the device easily interfaces Hall sensors, resolver feedback, and gate drivers. The 164-MBGA package is only 8 x 8 mm, enabling compact control PCBs. The 1.2 V core plus separate bank I/O supplies let the FPGA drive 3.3 V gate drivers directly. Quartus Prime Qsys simplifies peripheral integration for variable-frequency drives up to several kW.
おすすめ
Video Bridging and Image Aggregation
The 10CL016YM164C6G is well suited to entry-level video bridging tasks such as MIPI-CSI2 to parallel RGB conversion or HDMI auxiliary-channel processing. Its 516 Kb of embedded block memory provides line buffering without external SRAM, while the 56 multipliers handle color-space conversion and scaling math. The 87 user I/Os accept multiple 8/16-bit camera interfaces simultaneously. The 60 nm low-power process keeps the 1.2 V core consumption under 1 W for typical 1080p pipelines, making passive heatsink designs feasible in compact embedded vision modules.
おすすめ
Low-Cost Protocol Bridging
The 10CL016YM164C6G excels at bridging low-speed legacy protocols (UART, SPI, I2C, GPIO) to high-speed links such as Ethernet, USB, or PCIe soft IP. With 15,408 LEs the device can implement full TCP/IP offload, custom serial framing, and timestamp logic in a single chip, replacing multiple discrete MCUs and glue logic. The 87 I/Os are more than enough for quad-UART, octal-SPI slave, and parallel bus aggregation. Cyclone 10 LP's hardened PCI Express Gen1 IP block reduces soft-logic footprint for low-bandwidth endpoint applications.
おすすめ
Sensor Aggregation Hubs
The 10CL016YM164C6G aggregates sensor data from multiple sources such as IMUs, environmental sensors, and analog front ends in IoT edge nodes. Its 56 DSP blocks perform on-chip FFT, Kalman filtering, and signal conditioning in real time, while the 516 Kb of block RAM serves as circular buffer storage. The 87 I/Os accept SPI, I2C, and LVDS sensor buses concurrently. The commercial-grade 0-85C operating range suits indoor smart-building deployments, and the 164-MBGA package enables very small hub PCBs with passive cooling.
おすすめ
Entry-Level Software-Defined Radio
The 10CL016YM164C6G can implement narrow-band SDR front-ends for amateur radio, industrial telemetry, and sub-GHz wireless protocols. The 56 DSP multipliers enable digital down-conversion and channelization, and the LVDS-capable I/Os interface directly to ADC/DAC sample clocks. The hardened memory controller supports DDR3 sample buffers up to several hundred MSPS. Compared to a discrete DSP+ASIC design, this single-chip approach reduces BOM cost and PCB area significantly for sub-$200 radio products.
おすすめ
Automotive Infotainment Auxiliary Logic
The 10CL016YM164A7G (automotive-grade variant of this device) fits automotive infotainment auxiliary logic such as LVDS display bridging, CAN-FD message routing, and touch-panel interfacing. The 15,408 LEs handle message arbitration, audio routing, and backlight control. The 164-MBGA package survives the -40C to +125C automotive temperature range. Combined with the hardened PCI Express Gen1 IP, this device serves as a flexible companion to the main application processor in head-unit designs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10CL016YM164C6G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10CL016YM164A7G | 10CL016YM164I7G | 10CL016YM164C8G | 10CL010YM164C6G | 10CL010YM164C8G | 10CL010YM164I7G |
|---|---|---|---|---|---|---|---|
| Package | 164-MBGA (TFBGA, 8 x 8 mm) | 164-MBGA (TFBGA) - same | 164-MBGA (TFBGA) - same | 164-MBGA (TFBGA) - same | 164-MBGA (TFBGA) - same | 164-MBGA (TFBGA) - same | 164-MBGA (TFBGA) - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 15,408 | 15,408 | 15,408 | 15,408 | 10,320 | 10,320 | 10,320 |
| Embedded Memory | 516,096 bits | 516,096 bits | 516,096 bits | 516,096 bits | 414,720 bits | 414,720 bits | 414,720 bits |
| Temperature Grade | Commercial (0C to 85C) | Automotive (-40C to +125C) | Industrial (-40C to +100C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Commercial (0C to 85C) | Industrial (-40C to +100C) |
| Speed Grade | C6 (commercial, speed grade 6) | A7 (automotive, speed grade 7) | I7 (industrial, speed grade 7) | C8 (commercial, speed grade 8) | C6 (commercial, speed grade 6) | C8 (commercial, speed grade 8) | I7 (industrial, speed grade 7) |
| DSP Blocks (18x18) | 56 | 56 | 56 | 56 | 46 | 46 | 46 |
| User I/O Pins | 87 | 87 | 87 | 87 | 87 | 87 | 87 |
| Core Voltage | 1.2 V (1.15-1.25 V) | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
主な差別化要因
- Highest logic density in the 164-MBGA Cyclone 10 LP family （vs 10CL010YM164C6G)
- Commercial temperature grade with lowest cost position （vs 10CL016YM164I7G)
- Optimized speed grade 6 for typical designs （vs 10CL016YM164C8G)
設計ノート
Estimated: At 50% logic utilization and 100 MHz toggle rate, the Cyclone 10 LP core draws approximately 0.5-1.0 W from the 1.2 V rail. Provide a low-noise LDO (such as TI TPS7A4701 or similar) for VCCINT and a separate 2.5 V/3.3 V regulator for VCCIO bank supplies. Decoupling: place 0.1 uF X7R ceramic capacitors on every VCC pin within 5 mm trace length, plus 4.7 uF bulk capacitors at each supply plane. The PLL analog supply (VCCA_PLL) requires additional filtering per the device handbook.
The 164-MBGA package has theta_JA of approximately 28 C/W on a standard 4-layer JEDEC test board. Estimated: at 1.0 W dissipation, junction temperature rises 28 C above ambient, well within the 85 C commercial limit. Above 1.5 W dissipation, attach a thermal pad pattern on inner PCB layers to reduce theta_JB and keep junction temperature below 100 C. Industrial-grade variants (I7, A7) provide higher thermal headroom but follow the same board layout guidelines.
The 164-MBGA uses a 0.5 mm ball pitch. Per the Cyclone 10 LP hardware design guidelines, use microvia-in-pad construction with NSMD (non-solder-mask-defined) land pads of 0.30 mm diameter. Maintain a 0.20 mm solder mask clearance between adjacent pads. For high-speed LVDS or DDR3 interfaces, match trace lengths within 50 mil tolerance and use 100 ohm differential impedance. Reference the device pin connection guidelines for ball map and bank assignment details.
Do not leave VCCIO bank supplies floating - every active bank requires its own supply even if its I/Os are unused. The configuration pins (MSEL, nCONFIG, CONF_DONE) must be pulled to valid logic levels via 4.7 kohm resistors per the handbook. When migrating from Cyclone IV to Cyclone 10 LP, note that the JTAG pinout changed - verify against the pin connection guidelines, not Cyclone IV legacy documents. Avoid backdriving any configuration pin during power-up sequencing.
コンプライアンス情報
RoHS and REACH compliant per Intel product declaration. Lead-free (Pb-free) and halogen-free molding compound. Not AEC-Q100 qualified - choose 10CL016YM164A7G automotive variant for AEC-Q100 compliance.
