10CL010YM164C8G - Cyclone 10 LP FPGA, 10K LE, 164-MBGA | Intel
MPN: 10CL010YM164C8G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $21.41 | $21.41 |
| 10 | $19.85 | $198.50 |
| 100 | $16.9 | $1,690.00 |
| 500 | $14.25 | $7,125.00 |
| 1,000 | $12.1 | $12,100.00 |
Drop-in alternatives for 10CL010YM164C8G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet β10CL010YM164C8G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 LP |
| Logic Elements | 10,320 |
| Embedded Memory | 414 Kbit (M9K blocks) |
| Embedded 18x18 Multipliers | 56 |
| PLLs | 4 |
| Maximum User I/Os | 224 |
| Process Node | TSMC 60 nm low-power |
| Core Voltage | 1.0 V nominal (range 1.0 V to 1.1 V) |
| Speed Grade | -8C (commercial, 8 speed grade) |
| Package | 164-ball MBGA (Micro BGA, 8x8 mm) |
| Operating Junction Temperature | 0 C to +85 C (commercial) |
| Configuration Method | SRAM-based, JTAG/AS/AP/PS |
| Transceivers | None (general-purpose FPGA, no high-speed SERDES) |
| Hard PCIe Controller | 1x PCIe Gen1 (x1/x2 root port or endpoint) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| MSL Level | 3 (per JEDEC J-STD-020) |
| Lead-Free | Yes |
10CL010YM164C8G Pin Configuration
| Pin A1 | I/O β General-purpose user I/O bank 1 |
| Pin A2 | VCCIO1 β I/O bank 1 supply (1.2 V to 3.3 V) |
| Pin A3 | I/O β General-purpose user I/O bank 1 |
| Pin A4 | I/O β General-purpose user I/O bank 2 |
| Pin A5 | VCCIO2 β I/O bank 2 supply (1.2 V to 3.3 V) |
| Pin A6 | I/O β General-purpose user I/O bank 2 |
| Pin A7 | GND β Ground reference |
| Pin A8 | VCCINT β Core supply 1.0 V nominal |
| Pin A9 | I/O β General-purpose user I/O bank 3 |
| Pin A10 | VCCIO3 β I/O bank 3 supply (1.2 V to 3.3 V) |
| Pin A11 | I/O β General-purpose user I/O bank 3 |
| Pin B1 | I/O β General-purpose user I/O bank 1 |
| Pin B2 | GND β Ground reference |
| Pin B3 | I/O β General-purpose user I/O bank 1 |
| Pin B4 | VCCPD1 β Pre-driver supply 2.5 V / 3.3 V bank 1 |
| Pin B5 | I/O β General-purpose user I/O bank 2 |
| Pin B6 | GND β Ground reference |
| Pin B7 | I/O β General-purpose user I/O bank 2 |
| Pin B8 | VCCAUX β Auxiliary supply 2.5 V |
| Pin B9 | I/O β General-purpose user I/O bank 3 |
| Pin B10 | GND β Ground reference |
| Pin B11 | I/O β General-purpose user I/O bank 3 |
| Pin C1 | VCCIO1 β I/O bank 1 supply (1.2 V to 3.3 V) |
| Pin C2 | I/O β General-purpose user I/O bank 1 |
| Pin C3 | GND β Ground reference |
| Pin C4 | I/O β General-purpose user I/O bank 1 |
| Pin C5 | VCCIO2 β I/O bank 2 supply (1.2 V to 3.3 V) |
| Pin C6 | I/O β General-purpose user I/O bank 2 |
| Pin C7 | GND β Ground reference |
| Pin C8 | I/O β General-purpose user I/O bank 3 |
| Pin C9 | VCCIO3 β I/O bank 3 supply (1.2 V to 3.3 V) |
| Pin C10 | I/O β General-purpose user I/O bank 3 |
| Pin C11 | GND β Ground reference |
| Pin D1 | I/O β General-purpose user I/O bank 1 |
| Pin D2 | GND β Ground reference |
| Pin D3 | I/O β General-purpose user I/O bank 1 |
| Pin D4 | VCCINT β Core supply 1.0 V nominal |
| Pin D5 | GND β Ground reference |
| Pin D6 | I/O β General-purpose user I/O bank 2 |
| Pin D7 | VCCPD2 β Pre-driver supply 2.5 V / 3.3 V bank 2 |
| Pin D8 | I/O β General-purpose user I/O bank 3 |
| Pin D9 | GND β Ground reference |
| Pin D10 | I/O β General-purpose user I/O bank 3 |
| Pin D11 | I/O β General-purpose user I/O bank 3 |
| Pin E1 | I/O β General-purpose user I/O bank 4 |
| Pin E2 | VCCIO4 β I/O bank 4 supply (1.2 V to 3.3 V) |
| Pin E3 | I/O β General-purpose user I/O bank 4 |
| Pin E4 | I/O β General-purpose user I/O bank 4 |
| Pin E5 | VCCIO5 β I/O bank 5 supply (1.2 V to 3.3 V) |
| Pin E6 | I/O β General-purpose user I/O bank 5 |
| Pin E7 | GND β Ground reference |
| Pin E8 | VCCINT β Core supply 1.0 V nominal |
| Pin E9 | I/O β General-purpose user I/O bank 6 |
| Pin E10 | VCCIO6 β I/O bank 6 supply (1.2 V to 3.3 V) |
| Pin E11 | I/O β General-purpose user I/O bank 6 |
| Pin F1 | I/O β General-purpose user I/O bank 4 |
| Pin F2 | GND β Ground reference |
| Pin F3 | I/O β General-purpose user I/O bank 4 |
| Pin F4 | VCCPD4 β Pre-driver supply 2.5 V / 3.3 V bank 4 |
| Pin F5 | I/O β General-purpose user I/O bank 5 |
| Pin F6 | GND β Ground reference |
| Pin F7 | I/O β General-purpose user I/O bank 5 |
| Pin F8 | VCCAUX β Auxiliary supply 2.5 V |
| Pin F9 | I/O β General-purpose user I/O bank 6 |
| Pin F10 | GND β Ground reference |
| Pin F11 | I/O β General-purpose user I/O bank 6 |
| Pin G1 | VCCIO4 β I/O bank 4 supply (1.2 V to 3.3 V) |
| Pin G2 | I/O β General-purpose user I/O bank 4 |
| Pin G3 | GND β Ground reference |
| Pin G4 | I/O β General-purpose user I/O bank 4 |
| Pin G5 | VCCIO5 β I/O bank 5 supply (1.2 V to 3.3 V) |
| Pin G6 | I/O β General-purpose user I/O bank 5 |
| Pin G7 | GND β Ground reference |
| Pin G8 | I/O β General-purpose user I/O bank 6 |
| Pin G9 | VCCIO6 β I/O bank 6 supply (1.2 V to 3.3 V) |
| Pin G10 | I/O β General-purpose user I/O bank 6 |
| Pin G11 | GND β Ground reference |
| Pin H1 | I/O β General-purpose user I/O bank 4 |
| Pin H2 | GND β Ground reference |
| Pin H3 | I/O β General-purpose user I/O bank 4 |
| Pin H4 | VCCINT β Core supply 1.0 V nominal |
| Pin H5 | GND β Ground reference |
| Pin H6 | I/O β General-purpose user I/O bank 5 |
| Pin H7 | VCCPD5 β Pre-driver supply 2.5 V / 3.3 V bank 5 |
| Pin H8 | I/O β General-purpose user I/O bank 6 |
| Pin H9 | GND β Ground reference |
| Pin H10 | I/O β General-purpose user I/O bank 6 |
| Pin H11 | I/O β General-purpose user I/O bank 6 |
| Pin J1 | I/O β General-purpose user I/O bank 7 |
| Pin J2 | VCCIO7 β I/O bank 7 supply (1.2 V to 3.3 V) |
| Pin J3 | I/O β General-purpose user I/O bank 7 |
| Pin J4 | I/O β General-purpose user I/O bank 7 |
| Pin J5 | VCCIO8 β I/O bank 8 supply (1.2 V to 3.3 V) |
| Pin J6 | I/O β General-purpose user I/O bank 8 |
| Pin J7 | GND β Ground reference |
| Pin J8 | VCCINT β Core supply 1.0 V nominal |
| Pin J9 | I/O β General-purpose user I/O bank 8 |
| Pin J10 | VCCPD8 β Pre-driver supply 2.5 V / 3.3 V bank 8 |
| Pin J11 | I/O β General-purpose user I/O bank 8 |
| Pin K1 | I/O β General-purpose user I/O bank 7 |
| Pin K2 | GND β Ground reference |
| Pin K3 | I/O β General-purpose user I/O bank 7 |
| Pin K4 | VCCPD7 β Pre-driver supply 2.5 V / 3.3 V bank 7 |
| Pin K5 | I/O β General-purpose user I/O bank 8 |
| Pin K6 | GND β Ground reference |
| Pin K7 | I/O β General-purpose user I/O bank 8 |
| Pin K8 | VCCAUX β Auxiliary supply 2.5 V |
| Pin K9 | I/O β General-purpose user I/O bank 8 |
| Pin K10 | GND β Ground reference |
| Pin K11 | I/O β General-purpose user I/O bank 8 |
| Pin L1 | VCCIO7 β I/O bank 7 supply (1.2 V to 3.3 V) |
| Pin L2 | I/O β General-purpose user I/O bank 7 |
| Pin L3 | GND β Ground reference |
| Pin L4 | I/O β General-purpose user I/O bank 7 |
| Pin L5 | VCCIO8 β I/O bank 8 supply (1.2 V to 3.3 V) |
| Pin L6 | I/O β General-purpose user I/O bank 8 |
| Pin L7 | GND β Ground reference |
| Pin L8 | I/O β General-purpose user I/O bank 8 |
| Pin L9 | VCCINT β Core supply 1.0 V nominal |
| Pin L10 | I/O β General-purpose user I/O bank 8 |
| Pin L11 | GND β Ground reference |
| Pin M1 | I/O β General-purpose user I/O bank 7 |
| Pin M2 | GND β Ground reference |
| Pin M3 | I/O β General-purpose user I/O bank 7 |
| Pin M4 | VCCINT β Core supply 1.0 V nominal |
| Pin M5 | GND β Ground reference |
| Pin M6 | I/O β General-purpose user I/O bank 8 |
| Pin M7 | VCCAUX β Auxiliary supply 2.5 V |
| Pin M8 | I/O β General-purpose user I/O bank 8 |
| Pin M9 | GND β Ground reference |
| Pin M10 | I/O β General-purpose user I/O bank 8 |
| Pin M11 | I/O β General-purpose user I/O bank 8 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL010YM164C8G is suitable for 6 applications: Industrial I/O Expansion Module, Video Format Bridge / Image Sensor Pre-Processing, Motor Drive and Robotics Glue Logic, Telecom Line-Card Glue and Protocol Conversion, Low-Cost PCIe-Over-Cable Bridge, Battery-Powered Test & Measurement Instrumentation.
Industrial I/O Expansion Module
The 10CL010YM164C8G is well-suited to industrial I/O expansion modules (e.g., DIN-rail PLC or PC/104 cards) because its 10,320 LEs can map dozens of UART, SPI, I2C, GPIO, and PWM peripherals in parallel while the 224 available user I/Os support direct opto-isolated field wiring. The 1.0 V low-power core and 60 nm process keep typical power budgets under 1.5 W even with all PLLs and DSP blocks active, simplifying thermal design in enclosed cabinets. Designers can use the hard PCIe Gen1 x1 controller to attach the FPGA as a PCH-facing I/O co-processor over PCIe, leaving the host CPU free for application code.
Recommended
Video Format Bridge / Image Sensor Pre-Processing
In machine-vision and image-sensor front ends, the 10CL010YM164C8G can ingest parallel CMOS sensor data (e.g., MIPI CSI-2 over LVDS or sub-LVDS) and reformat it to HDMI, BT.656, USB3 Vision, or Ethernet AVB streams. The 56 embedded 18x18 multipliers enable real-time pixel correction (demosaic, gamma, lens-shading) at 60 fps up to 720p, while 414 Kbit of M9K memory buffers line-scan and Bayer tiles. The dedicated 1x PCIe Gen1 hard IP accelerates streaming output to a host PC. Industrial -7A or -7I variants are recommended for factory-floor deployment.
Recommended
Motor Drive and Robotics Glue Logic
The 10CL010YM164C8G is a strong fit as glue logic between a microcontroller/DSP and a 3-phase motor inverter: it implements field-oriented control (FOC) commutation tables, encoder quadrature decoding, hall-sensor debouncing, and safety interlocks with deterministic sub-microsecond latency. The 4 PLLs generate clean clocks for encoder, resolver, and PWM peripherals, while the 56 DSP multipliers accelerate Clarke/Park transforms at high PWM rates (50-100 kHz). Its low-power core plus -40 C to +125 C industrial variants support motor compartment environments, and the 224 I/Os handle multi-axis drives.
Recommended
Telecom Line-Card Glue and Protocol Conversion
In telecom line cards, the 10CL010YM164C8G bridges legacy TDM (E1/T1/J1) framers to modern packet backplanes, offloading the host CPU. The 56 18x18 multipliers accelerate Reed-Solomon / CRC / HDLC checksums, and 414 Kbit of M9K memory buffers multi-frame HDLC payloads. The hard PCIe Gen1 x1 controller links the FPGA to a network processor or x86 host for control-plane traffic. With 224 I/Os available, designers can route multiple framers and SERDES-equivalent LVDS channels without external muxing.
Recommended
Low-Cost PCIe-Over-Cable Bridge
The 10CL010YM164C8G integrates a hard PCIe Gen1 (x1/x2) controller, making it ideal for cost-sensitive PCIe-over-cable adapters that extend PCIe across Ethernet or coax backplanes. Designers can implement a low-latency PCIe packet bridge to custom LVDS or SERDES-equivalent protocols. Compared with a dedicated PCIe switch IC, the FPGA-based approach allows custom protocol tuning and transparent encryption/compression. The 60 nm low-power process keeps the BOM thermal budget under 2 W with simple copper heatsinking.
Recommended
Battery-Powered Test & Measurement Instrumentation
Battery-powered oscilloscope probes, logic analyzers, and field-portable data loggers benefit from the 10CL010YM164C8G's low static and dynamic power at 1.0 V core - typically <0.5 W in mid-utilization scenarios. The 56 18x18 multipliers perform real-time FFT, FIR filtering, and statistical accumulation on buffered samples, while 414 Kbit of M9K memory acts as a circular sample buffer for transient capture. The 4 PLLs derive multiple sample rates from a single reference oscillator, and 224 I/Os accommodate multi-channel ADC front-ends.
Recommended
Recommended Products Summary
Engineering reference data for 10CL010YM164C8G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL010YM164C6G | 10CL010YM164A7G | 10CL010YM164I7G | 10CL010YM164C8G | 10CL016YM164C8G |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 164-ball MBGA (8x8 mm) | 164-ball MBGA - same | 164-ball MBGA - same | 164-ball MBGA - same | 164-ball MBGA - same | 164-ball MBGA - same |
| Logic Elements | 10,320 | 10,320 | 10,320 | 10,320 | 10,320 | 15,408 (+50%) |
| Embedded Memory | 414 Kbit | 414 Kbit | 414 Kbit | 414 Kbit | 414 Kbit | 504 Kbit |
| Speed Grade | -8C (commercial) | -6C (commercial, lower Fmax) | -7A (automotive grade) | -7I (industrial grade) | -8C (commercial) | -8C (commercial) |
| Operating Junction Temperature | 0 C to +85 C | 0 C to +85 C | -40 C to +125 C | -40 C to +100 C | 0 C to +85 C | 0 C to +85 C |
| Embedded Multipliers (18x18) | 56 | 56 | 56 | 56 | 56 | 56 |
| Hard PCIe Controller | Yes (Gen1 x1/x2) | Yes (Gen1 x1/x2) | Yes (Gen1 x1/x2) | Yes (Gen1 x1/x2) | Yes (Gen1 x1/x2) | Yes (Gen1 x1/x2) |
| Unit Price (1-piece break) | $21.41 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest speed grade in the 10K-LE 164-MBGA variant (vs 10CL010YM164C6G)
- In-family logic capacity upgrade path on identical footprint (vs 10CL016YM164C8G)
- Hard PCIe Gen1 controller eliminates soft IP overhead (vs Lattice ECP5 (LFE5U-12F-8BG256C) in similar footprint)
Design Notes
Estimated: at typical 60% LE utilization, 50% toggle rate, and 25 C ambient, the 10CL010YM164C8G core draws approximately 0.6-0.9 W from the 1.0 V VCCINT rail. Provide at least 1.5 A VCCINT headroom and use a low-noise LDO (e.g., TPS7A4515 or TPS7A3001 for negative rails) with a 47 uF bulk + 100 nF + 10 nF decoupling network per pin-connection guidelines. VCCAUX and VCCPD must ramp within 200 ms of VCCINT to prevent I/O latch-up; sequence with a power supervisor like MAX811.
Estimated: the 164-ball MBGA uses a 0.5 mm ball pitch with 8x8 mm body. Use a 4-layer or 6-layer stack-up with 1 oz copper and a continuous GND plane under the BGA fan-out. Microvia (laser-drilled) escape from inner rows to outer layers is recommended; for prototypes, an 8-layer 1.0 oz stack with 0.8 mm core and 0.1 mm prepreg works well. Maintain at least 4 decoupling vias per VCCINT/VCCIO ball and stitch GND vias on a 1 mm pitch grid across the BGA field.
Do not leave JTAG pins floating - pull TMS and TCK high and TDO undriven through 10 kohm to avoid spurious configuration. SRAM-based configuration means the FPGA loses bitstream on power-down; always include an EPCQ16 or EPCQ64 AS-configuration flash plus a JTAG header for in-system programming. Avoid sharing VCCIO bank voltages across incompatible I/O standards (e.g., do not mix 2.5 V LVCMOS and 1.8 V SSTL on the same bank without bank-level isolation).
Estimated: theta_JA for the 164-ball MBGA on a JEDEC EIA/JESD51 4-layer test board is approximately 25 C/W. With 0.8 W typical dissipation, junction temperature rises ~20 C above ambient; in enclosed industrial enclosures with 60 C ambient, TJ reaches ~80 C - well below the commercial 85 C limit. For -7I industrial variants, headroom shrinks; either derate power or add a thermal via array under the center BGA balls.
Compliance Information
RoHS-compliant per Altera/Intel product page. MSL 3 per JEDEC J-STD-020. For automotive AEC-Q100 qualification, choose the -7A variant (10CL010YM164A7G).
