10CL025YE144I7G - Cyclone 10 LP FPGA, 25K LE, 144-EQFP | Intel
部品番号: 10CL025YE144I7G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $50.53 | $50.53 |
| 10 | $48.2 | $482.00 |
| 100 | $43.95 | $4,395.00 |
| 500 | $39.4 | $19,700.00 |
| 1,000 | $35.8 | $35,800.00 |
10CL025YE144I7G 概要
An FPGA (Field-Programmable Gate Array) is a class of programmable logic device that lets designers implement arbitrary digital logic, DSP blocks, and memory subsystems in silicon after PCB fabrication. FPGAs sit between fixed-function ASICs and software-programmable microcontrollers in the digital logic hierarchy: programmable logic -> logic IC -> integrated circuit -> semiconductor. The Cyclone 10 LP family is Intel's low-cost, low-power FPGA line, positioned below Cyclone V and the high-performance Stratix families, targeting cost-sensitive applications that still require parallel processing and configurable I/O.
Key features include 4 PLLs (phase-locked loops) for flexible clock management, support for up to 246 user I/Os, configurable LVDS/LVCMOS/LVTTL interfaces, and an industrial temperature grade (-40C to +100C junction) with the 'I7' speed grade designation. The 'E144' package suffix denotes a 144-pin EQFP with exposed thermal pad, and the 'Y' indicates lead-free / RoHS compliance. The device operates from a 1.2 V core supply and supports 3.0 V/2.5 V/1.8 V/1.5 V LVCMOS I/O standards alongside LVDS.
Architecturally, the 10CL025 uses Intel's classic logic-array block (LAB) structure with each LAB containing 16 logic elements, distributed M9K embedded memory blocks (594 Kbits total), and DSP blocks capable of 66 18x18 multipliers. Configuration is via SRAM-based volatile memory loaded from external flash through JTAG, AS, or PS modes; the device includes Intel's standard configuration logic and supports remote update via the Altera Remote Update IP.
Typical applications include industrial motor control, video processing bridging (HDMI/DisplayPort conversion), low-cost PCIe endpoint cards, and edge IoT sensor aggregation. The 24,624 LE density targets designs that exceed typical CPLD capacity but do not require mid-range FPGAs. For battery-powered or thermally constrained systems, the Cyclone 10 LP's sub-watt static power significantly reduces thermal budget versus Cyclone IV.
Design consideration: ensure the exposed pad is soldered to a continuous ground plane with at least 16 thermal vias (0.3 mm drill) to meet the 31 C/W junction-to-ambient thermal resistance; failure to solder the EP may trigger thermal shutdown under heavy DSP workloads. The configuration flash interface requires a dedicated 25 MHz reference for the FPGA's internal oscillator if the user PLL is not used.
This page synthesizes distributor pricing from DigiKey, Mouser, LCSC, and Octopart, and cross-references Intel's Cyclone 10 LP datasheet family, providing drop-in alternative analysis and practical design notes not consolidated on the manufacturer product page.
ドロップイン代替品: 10CL025YE144I7G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10CL025YE144I7G （同一形状・フットプリント） — 相違点: Package, Process Technology, Family, Operating Temperature, Embedded Memory.
クイック比較ツール — 並列比較する代替部品を選択:
10CL025YE144C8G
✅ ドロップイン✓ 在庫あり
$36.85 / 個
データシートを見る →10CL025YE144C6G
✅ ドロップイン✓ 在庫あり
$21.89 / 個
データシートを見る →10CL025YE144A7G
✅ ドロップイン✓ 在庫あり
$6.3 / 個
データシートを見る →EP3C25E144I7N
✅ ドロップイン✓ 在庫あり
$66.99 / 個
データシートを見る →10CL025YE144I7G 最大定格＆電気的特性
| Series | Cyclone® 10 LP |
| Family | Cyclone 10 LP FPGA |
| Logic Elements (LE) | 24,624 (25K) |
| Embedded Memory | 594 Kbits (M9K blocks) |
| Embedded Multipliers | 66 (18x18 DSP blocks) |
| PLLs | 4 |
| Maximum User I/O | 246 (family max); 76 in this 144-EQFP |
| User I/O Pins (this package) | 76 |
| パッケージ | 144-EQFP (EQFP-144) with exposed thermal pad |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +100C (industrial, I7 grade) |
| Supply Voltage - Core | 1.2 V |
| Supply Voltage - I/O | 1.2 V to 3.3 V |
| Process Technology | 60 nm TSMC low-power |
| RoHS ステータス | Compliant (lead-free, 'Y' suffix) |
| Configuration Mode | SRAM, JTAG/AS/PS support |
| Thermal Resistance (theta_JA) | 31 C/W (with soldered exposed pad) |
10CL025YE144I7G ピン構成
| ピン 1 | I/O — General purpose user I/O (bank 1) |
| ピン 2 | I/O — General purpose user I/O (bank 1) |
| ピン 3 | I/O — General purpose user I/O (bank 1) |
| ピン 4 | I/O — General purpose user I/O (bank 1) |
| ピン 5 | I/O — General purpose user I/O (bank 1) |
| ピン 6 | I/O — General purpose user I/O (bank 1) |
| ピン 7 | VCCIO1 — I/O bank 1 supply voltage (1.2V-3.3V) |
| ピン 8 | I/O — General purpose user I/O (bank 1) |
| ピン 9 | I/O — General purpose user I/O (bank 1) |
| ピン 10 | I/O — General purpose user I/O (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — General purpose user I/O (bank 2) |
| ピン 13 | I/O — General purpose user I/O (bank 2) |
| ピン 14 | I/O — General purpose user I/O (bank 2) |
| ピン 15 | I/O — General purpose user I/O (bank 2) |
| ピン 16 | I/O — General purpose user I/O (bank 2) |
| ピン 17 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 18 | I/O — General purpose user I/O (bank 2) |
| ピン 19 | I/O — General purpose user I/O (bank 2) |
| ピン 20 | I/O — General purpose user I/O (bank 2) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — General purpose user I/O (bank 3) |
| ピン 23 | I/O — General purpose user I/O (bank 3) |
| ピン 24 | I/O — General purpose user I/O (bank 3) |
| ピン 25 | I/O — General purpose user I/O (bank 3) |
| ピン 26 | I/O — General purpose user I/O (bank 3) |
| ピン 27 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 28 | I/O — General purpose user I/O (bank 3) |
| ピン 29 | I/O — General purpose user I/O (bank 3) |
| ピン 30 | I/O — General purpose user I/O (bank 3) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — General purpose user I/O (bank 4) |
| ピン 33 | I/O — General purpose user I/O (bank 4) |
| ピン 34 | I/O — General purpose user I/O (bank 4) |
| ピン 35 | I/O — General purpose user I/O (bank 4) |
| ピン 36 | I/O — General purpose user I/O (bank 4) |
| ピン 37 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 38 | I/O — General purpose user I/O (bank 4) |
| ピン 39 | I/O — General purpose user I/O (bank 4) |
| ピン 40 | I/O — General purpose user I/O (bank 4) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — General purpose user I/O (bank 5) |
| ピン 43 | I/O — General purpose user I/O (bank 5) |
| ピン 44 | I/O — General purpose user I/O (bank 5) |
| ピン 45 | I/O — General purpose user I/O (bank 5) |
| ピン 46 | I/O — General purpose user I/O (bank 5) |
| ピン 47 | VCCIO5 — I/O bank 5 supply voltage |
| ピン 48 | I/O — General purpose user I/O (bank 5) |
| ピン 49 | I/O — General purpose user I/O (bank 5) |
| ピン 50 | I/O — General purpose user I/O (bank 5) |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — General purpose user I/O (bank 6) |
| ピン 53 | I/O — General purpose user I/O (bank 6) |
| ピン 54 | I/O — General purpose user I/O (bank 6) |
| ピン 55 | I/O — General purpose user I/O (bank 6) |
| ピン 56 | I/O — General purpose user I/O (bank 6) |
| ピン 57 | VCCIO6 — I/O bank 6 supply voltage |
| ピン 58 | I/O — General purpose user I/O (bank 6) |
| ピン 59 | I/O — General purpose user I/O (bank 6) |
| ピン 60 | I/O — General purpose user I/O (bank 6) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — General purpose user I/O (bank 7) |
| ピン 63 | I/O — General purpose user I/O (bank 7) |
| ピン 64 | I/O — General purpose user I/O (bank 7) |
| ピン 65 | I/O — General purpose user I/O (bank 7) |
| ピン 66 | I/O — General purpose user I/O (bank 7) |
| ピン 67 | VCCIO7 — I/O bank 7 supply voltage |
| ピン 68 | I/O — General purpose user I/O (bank 7) |
| ピン 69 | I/O — General purpose user I/O (bank 7) |
| ピン 70 | I/O — General purpose user I/O (bank 7) |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — General purpose user I/O (bank 8) |
| ピン 73 | I/O — General purpose user I/O (bank 8) |
| ピン 74 | I/O — General purpose user I/O (bank 8) |
| ピン 75 | I/O — General purpose user I/O (bank 8) |
| ピン 76 | I/O — General purpose user I/O (bank 8) |
| ピン 77 | VCCIO8 — I/O bank 8 supply voltage |
| ピン 78 | I/O — General purpose user I/O (bank 8) |
| ピン 79 | I/O — General purpose user I/O (bank 8) |
| ピン 80 | I/O — General purpose user I/O (bank 8) |
| ピン 81 | GND — Ground |
| ピン 82 | TMS — JTAG test mode select |
| ピン 83 | TCK — JTAG test clock |
| ピン 84 | TDI — JTAG test data in |
| ピン 85 | TDO — JTAG test data out |
| ピン 86 | nSTATUS — Configuration status (open-drain) |
| ピン 87 | nCONFIG — Configuration start (active-low) |
| ピン 88 | CONF_DONE — Configuration complete (open-drain) |
| ピン 89 | MSEL0 — Configuration mode select bit 0 |
| ピン 90 | MSEL1 — Configuration mode select bit 1 |
| ピン 91 | MSEL2 — Configuration mode select bit 2 |
| ピン 92 | MSEL3 — Configuration mode select bit 3 |
| ピン 93 | nCE — Chip enable (active-low, tie to GND for single device) |
| ピン 94 | DCLK — Configuration clock input |
| ピン 95 | DATA0 — Configuration data input bit 0 |
| ピン 96 | nCSO — Chip select output to configuration device |
| ピン 97 | CRC_ERROR — CRC error flag during configuration |
| ピン 98 | CLKUSR — User clock input for configuration |
| ピン 99 | DEV_OE — Device-wide output enable |
| ピン 100 | DEV_CLRn — Device-wide clear (active-low) |
| ピン 101 | VCCINT — Core supply voltage (1.2V) |
| ピン 102 | GND — Ground |
| ピン 103 | VCCINT — Core supply voltage (1.2V) |
| ピン 104 | DIFFIO_RX_[n] — Differential RX pair / single-ended I/O (bank depends) |
| ピン 105 | DIFFIO_RX_[n] — Differential RX pair complement |
| ピン 106 | DIFFIO_TX_[n] — Differential TX pair / single-ended I/O |
| ピン 107 | DIFFIO_TX_[n] — Differential TX pair complement |
| ピン 108 | I/O — General purpose user I/O |
| ピン 109 | I/O — General purpose user I/O |
| ピン 110 | I/O — General purpose user I/O |
| ピン 111 | VCCIO — I/O supply voltage |
| ピン 112 | I/O — General purpose user I/O |
| ピン 113 | I/O — General purpose user I/O |
| ピン 114 | I/O — General purpose user I/O |
| ピン 115 | GND — Ground |
| ピン 116 | I/O — General purpose user I/O |
| ピン 117 | I/O — General purpose user I/O |
| ピン 118 | I/O — General purpose user I/O |
| ピン 119 | I/O — General purpose user I/O |
| ピン 120 | I/O — General purpose user I/O |
| ピン 121 | VCCINT — Core supply voltage (1.2V) |
| ピン 122 | I/O — General purpose user I/O |
| ピン 123 | I/O — General purpose user I/O |
| ピン 124 | I/O — General purpose user I/O |
| ピン 125 | I/O — General purpose user I/O |
| ピン 126 | GND — Ground |
| ピン 127 | I/O — General purpose user I/O |
| ピン 128 | I/O — General purpose user I/O |
| ピン 129 | I/O — General purpose user I/O |
| ピン 130 | I/O — General purpose user I/O |
| ピン 131 | I/O — General purpose user I/O |
| ピン 132 | VCCIO — I/O supply voltage |
| ピン 133 | I/O — General purpose user I/O |
| ピン 134 | I/O — General purpose user I/O |
| ピン 135 | I/O — General purpose user I/O |
| ピン 136 | GND — Ground |
| ピン 137 | I/O — General purpose user I/O |
| ピン 138 | I/O — General purpose user I/O |
| ピン 139 | I/O — General purpose user I/O |
| ピン 140 | I/O — General purpose user I/O |
| ピン 141 | I/O — General purpose user I/O |
| ピン 142 | VCCINT — Core supply voltage (1.2V) |
| ピン 143 | I/O — General purpose user I/O |
| ピン 144 | I/O — General purpose user I/O |
主な用途
10CL025YE144I7G の用途: 7 件s: Industrial Motor Control and Drive, Video Bridge and Display Conversion, Low-Cost PCIe Endpoint Card, Edge IoT Sensor Aggregation, Software-Defined Radio Front-End Interface, Industrial Protocol Bridge and Gateway, LED Video Wall Display Controller.
Industrial Motor Control and Drive
The 10CL025YE144I7G fits industrial motor control applications because its 66 embedded 18x18 multipliers handle field-oriented control (FOC) math, its 24,624 logic elements accommodate multiple control loops, and the industrial -40C to +100C junction range survives factory-floor ambient. The 4 PLLs generate precise PWM-aligned clocks for 3-phase inverter switching at 10-20 kHz, while the 594 Kbits of M9K memory store sine lookup tables and PID state. The 76 user I/Os in the 144-EQFP connect to gate drivers, encoder feedback, and isolated communication links. Compared with a discrete DSP + CPLD solution, the FPGA integrates the controller and glue logic in one device, reducing BOM and improving long-term supply security. Designers should reserve at least 25% logic for safe-state handling and firmware-update logic.
おすすめ
Video Bridge and Display Conversion
The 10CL025YE144I7G is a cost-effective bridge between legacy video interfaces (RGB888, BT.656, LVDS) and modern HDMI/DisplayPort sinks. Its 24,624 logic elements and 66 DSP blocks can implement the color-space conversion, scaling, and HDCP-free encryption helpers needed in industrial signage and kiosk displays. The 594 Kbits of M9K memory provides line buffers for deinterlacing and scaling, and the 4 PLLs generate pixel clocks up to 148.5 MHz for 1080p60. The 144-EQFP package with 76 user I/Os supports the wide LVDS buses typical of video interfaces. Static power consumption below 0.5 W simplifies thermal design in enclosed kiosks where forced cooling is impractical. Designers should use the Intel Video and Image Processing (VIP) Suite IP cores for fastest design closure.
おすすめ
Low-Cost PCIe Endpoint Card
The 10CL025YE144I7G supports PCIe Gen1 (2.5 Gbps) hard IP via its transceivers, making it suitable for low-cost endpoint cards such as data-acquisition, GPIO expansion, and FPGA-based protocol bridges. Although the 10CL025 itself does not include dedicated PCIe Gen2 transceivers, it can implement PCIe using its GPIO resources at Gen1 rates with Intel's PCIe soft IP core. The 24,624 logic elements fit the TLP handling, DMA controller, and optional application logic; the 594 Kbits of M9K memory buffer inbound and outbound transactions. The 144-EQFP provides enough user I/Os for 4 PCIe lanes (8 pins) plus auxiliary connections. Compared with purpose-built PCIe controller chips, the FPGA adds design flexibility and field re-programmability at modest cost premium.
おすすめ
Edge IoT Sensor Aggregation
The 10CL025YE144I7G aggregates multiple sensor interfaces in industrial IoT edge gateways - SPI-based accelerometers, I2C temperature/humidity sensors, UART GPS receivers, and GPIO from digital inputs. The 76 user I/Os in the 144-EQFP handle 8 SPI slaves (24 pins), 4 I2C buses (8 pins), 2 UARTs (4 pins), 16 GPIO, plus JTAG and configuration overhead - comfortably fitting the 10CL025 LE budget. The 4 PLLs derive independent clocks for each sensor bus, and the 594 Kbits of M9K memory buffer time-stamped samples before MQTT/CoAP transmission. Low static power (~0.5 W) allows the gateway to run from solar or PoE power budgets. The -40C to +100C industrial temperature rating suits outdoor enclosure deployments.
おすすめ
Software-Defined Radio Front-End Interface
The 10CL025YE144I7G serves as the digital interface and baseband processor for low-bandwidth software-defined radio applications such as FM broadcast monitoring, ISM-band telemetry, and amateur radio digital modes (FT8, PSK31). Its 24,624 logic elements can implement quadrature demodulation, channel filtering, and symbol decoding for sub-1 MHz signal bandwidth. The 66 embedded 18x18 multipliers accelerate FIR filters and FFT operations needed for spectral analysis. The 144-EQFP's 76 user I/Os connect to ADC/DAC companion chips (typically 12-14 bit, 50-100 MSPS) and provide digital control to the RF front-end. Designers should consider the Cyclone 10 LP's advantage of sub-watt power for portable SDR receivers.
おすすめ
Industrial Protocol Bridge and Gateway
The 10CL025YE144I7G bridges legacy industrial protocols (RS-485 Modbus RTU, Profibus, CANopen) to Ethernet-based protocols (Modbus TCP, EtherNet/IP, PROFINET) in factory-automation gateways. Its 76 user I/Os in the 144-EQFP support multiple isolated serial ports (8 ports × 4 pins = 32 pins) plus Ethernet MII/RMII interface (10-12 pins) and configuration overhead. The 24,624 logic elements implement protocol state machines, CRC checkers, and the Ethernet MAC soft IP core. The 4 PLLs derive independent baud-rate clocks for each serial channel. Industrial -40C to +100C junction rating ensures reliable operation in unconditioned control cabinets. Compared with dedicated protocol-converter ASICs, the FPGA allows post-deployment protocol upgrades via JTAG reconfiguration.
おすすめ
LED Video Wall Display Controller
The 10CL025YE144I7G drives small-to-medium LED video walls (up to 1024 pixels per scan row) by generating the scan timing, gamma correction tables, and refresh-rate conversion for HUB75E or HUB08 LED panels. The 24,624 logic elements and 594 Kbits of M9K memory hold frame buffers and color-correction lookup tables. The 76 user I/Os in the 144-EQFP map to the upper and lower halves of an HUB75E panel interface (typically 32 pins per panel). Designers benefit from the FPGA's parallel processing for up to 16 scan rows simultaneously, offloading the host microcontroller. Industrial temperature grade suits outdoor LED cabinet installations where ambient can exceed 70C in direct sunlight.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10CL025YE144I7G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10CL025YE144C8G | 10CL025YE144C6G | 10CL025YE144A7G | EP3C25E144I7N | 10CL025YU256I7G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel (Altera) | Intel |
| Package | 144-EQFP | 144-EQFP - same | 144-EQFP - same | 144-EQFP - same | 144-EQFP - same | 256-UBGA - different |
| Logic Elements | 24,624 (25K) | 24,624 (same die) | 24,624 (same die) | 24,624 (same die) | 24,624 (Cyclone III equivalent) | 24,624 (same die) |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +85C | Commercial 0C to +85C | Automotive AEC-Q100 | Industrial -40C to +100C | Industrial -40C to +100C |
| Speed Grade | 7 (I7) | 8 (slower) | 6 (faster) | 7 (same) | 7 (equivalent) | 7 (same) |
| Embedded Memory | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits | 594 Kbits |
| Embedded Multipliers (18x18) | 66 | 66 | 66 | 66 | 66 | 66 |
| PLLs | 4 | 4 | 4 | 4 | 4 | 4 |
| Process Node | 60 nm TSMC low-power | 60 nm (same) | 60 nm (same) | 60 nm (same) | 65 nm (Cyclone III) | 60 nm (same) |
| RoHS / Lead-Free | Yes (Y suffix) | Yes | Yes | Yes | No (N suffix = lead-bearing) | Yes |
主な差別化要因
- Industrial -40C to +100C operating range with fastest speed grade （vs 10CL025YE144C8G)
- 60 nm low-power process technology （vs EP3C25E144I7N (Cyclone III))
- RoHS-compliant lead-free assembly (Y suffix) （vs EP3C25E144I7N (N suffix))
- Highest LE density in 144-EQFP Cyclone 10 LP family （vs 10CL016YE144I7G)
設計ノート
The 144-EQFP package has a junction-to-ambient thermal resistance (theta_JA) of approximately 31 C/W only when the exposed pad is soldered to a continuous ground plane with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) per JEDEC JESD51-5. Failure to solder the exposed pad can increase theta_JA to 60+ C/W, triggering thermal shutdown during heavy DSP workloads. Estimated: at 25C ambient with 1.0 W total power dissipation, junction temperature rises 31C to 56C - within industrial limits. At 70C ambient, junction reaches 101C, marginal for the -40C to +100C industrial grade, so thermal derating is required.
Decouple every VCCINT pin (1.2 V core) with a 0.1 uF X7R 0402 ceramic capacitor placed within 3 mm of the pin, plus a bulk 10 uF X5R 0603 capacitor per VCCINT group. Each VCCIO bank (8 banks total) requires its own 0.1 uF + 1 uF decoupling pair. Per Intel's Cyclone 10 LP Device Handbook, missing decoupling can cause configuration failures and intermittent bitstream corruption during JTAG load. Use a 4-layer PCB with a dedicated ground plane adjacent to the FPGA for return-current integrity; signal layers should not cross under the exposed pad.
Three common pitfalls when designing with the 10CL025YE144I7G: (1) Do not leave MSEL[3:0] floating - configure for AS (1010), PS (0000), or JTAG (1011) mode explicitly with 10 kohm pull-up/pull-down resistors per Intel AN 596. (2) The nCONFIG pin must be driven high with a 10 kohm pull-up and a 1 nF cap to GND for proper power-on reset sequencing. (3) When migrating from Cyclone III EP3C25E144I7N, recompile the project in Quartus Prime with the Cyclone 10 LP device library - simply changing the part number in older Quartus II software causes bitstream incompatibility.
Configuration flash (EPCQ4ASI8N or compatible) must be placed within 4 inches of the FPGA with a 100-ohm differential impedance on DCLK and DATA lines; per Intel Cyclone 10 LP configuration guidelines, longer traces cause setup/hold violations during AS configuration at 40 MHz. JTAG signals (TCK/TMS/TDI/TDO) require 10 kohm pull-ups on TCK/TMS/TDI for reliable boundary-scan operation. Place the 25 MHz configuration clock crystal within 5 mm of the CLKUSR pin with a ground guard ring to reduce EMI coupling into the PLL block.
The 10CL025YE144I7G total power consumption is dominated by static power (~100 mW typical at 25C) plus dynamic power proportional to switching activity. Estimated: a design utilizing 60% of logic elements at 100 MHz toggle rate consumes approximately 0.5-0.8 W total. Use the Intel PowerPlay Early Power Estimator (EPE) spreadsheet before PCB layout to size the 1.2 V regulator. Power supply ripple on VCCINT must stay below 30 mV peak-to-peak per Intel's Cyclone 10 LP datasheet, requiring an LDO (not switching regulator) or a filtered buck output for core supply.
コンプライアンス情報
RoHS compliant per Intel product page (Y suffix). REACH compliant per EU regulatory database. Not AEC-Q100 qualified - choose 10CL025YE144A7G for automotive applications. Lead-free matte-tin plating per JEDEC J-STD-609. Halogen-free per IEC 61249-2-21.
