10CL025YE144C8G - Cyclone 10 LP FPGA 25K LE, 144-EQFP | Intel
MPN: 10CL025YE144C8G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $63.41 | $63.41 |
| 10 | $58.2 | $582.00 |
| 100 | $49.75 | $4,975.00 |
| 500 | $42.3 | $21,150.00 |
| 1,000 | $36.85 | $36,850.00 |
Drop-in alternatives for 10CL025YE144C8G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →10CL025YE144C8G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 LP |
| Logic Elements (LE) | 24,624 |
| Embedded Memory | 608,256 bit (M9K blocks) |
| Embedded Multipliers (18x18) | 66 |
| Maximum User I/O | 76 |
| Package | 144-pin EQFP (22x22 mm, exposed pad) |
| Mounting Type | Surface Mount |
| Speed Grade | C8 |
| Operating Temperature | 0C to +85C (commercial) |
| Core Voltage (VCCINT) | 1.0 V to 1.2 V |
| I/O Voltage Banks | Multiple VCCIO banks supporting 1.2 V to 3.3 V |
| Configuration Modes | JTAG, Active Serial (AS), Passive Serial (PS) |
| PLL Count | 4 |
| Process Technology | 60 nm low-power |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes (per Cyclone 10 LP product family) |
10CL025YE144C8G Pin Configuration
| Pin 1 | I/O — General purpose user I/O (bank 1) |
| Pin 2 | I/O — General purpose user I/O (bank 1) |
| Pin 3 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 4 | I/O — General purpose user I/O (bank 1) |
| Pin 5 | I/O — General purpose user I/O (bank 1) |
| Pin 6 | I/O — General purpose user I/O (bank 1) |
| Pin 7 | I/O — General purpose user I/O (bank 1) |
| Pin 8 | I/O — General purpose user I/O (bank 1) |
| Pin 9 | I/O — General purpose user I/O (bank 2) |
| Pin 10 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 11 | I/O — General purpose user I/O (bank 2) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — General purpose user I/O (bank 2) |
| Pin 14 | I/O — General purpose user I/O (bank 2) |
| Pin 15 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 16 | GND — Ground |
| Pin 17 | I/O — General purpose user I/O (bank 3) |
| Pin 18 | I/O — General purpose user I/O (bank 3) |
| Pin 19 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 20 | I/O — General purpose user I/O (bank 3) |
| Pin 21 | I/O — General purpose user I/O (bank 3) |
| Pin 22 | I/O — General purpose user I/O (bank 3) |
| Pin 23 | I/O — General purpose user I/O (bank 4) |
| Pin 24 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 25 | I/O — General purpose user I/O (bank 4) |
| Pin 26 | I/O — General purpose user I/O (bank 4) |
| Pin 27 | GND — Ground |
| Pin 28 | I/O — General purpose user I/O (bank 4) |
| Pin 29 | I/O — General purpose user I/O (bank 5) |
| Pin 30 | I/O — General purpose user I/O (bank 5) |
| Pin 31 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 32 | I/O — General purpose user I/O (bank 5) |
| Pin 33 | I/O — General purpose user I/O (bank 5) |
| Pin 34 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 35 | GND — Ground |
| Pin 36 | I/O — General purpose user I/O (bank 5) |
| Pin 37 | I/O — General purpose user I/O (bank 6) |
| Pin 38 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 39 | I/O — General purpose user I/O (bank 6) |
| Pin 40 | I/O — General purpose user I/O (bank 6) |
| Pin 41 | I/O — General purpose user I/O (bank 6) |
| Pin 42 | I/O — General purpose user I/O (bank 7) |
| Pin 43 | VCCIO7 — I/O bank 7 supply voltage |
| Pin 44 | I/O — General purpose user I/O (bank 7) |
| Pin 45 | I/O — General purpose user I/O (bank 7) |
| Pin 46 | GND — Ground |
| Pin 47 | I/O — General purpose user I/O (bank 7) |
| Pin 48 | I/O — General purpose user I/O (bank 7) |
| Pin 49 | I/O — General purpose user I/O (bank 8) |
| Pin 50 | VCCIO8 — I/O bank 8 supply voltage |
| Pin 51 | I/O — General purpose user I/O (bank 8) |
| Pin 52 | I/O — General purpose user I/O (bank 8) |
| Pin 53 | I/O — General purpose user I/O (bank 8) |
| Pin 54 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 55 | GND — Ground |
| Pin 56 | I/O — General purpose user I/O (bank 8) |
| Pin 57 | I/O — General purpose user I/O (bank 9) |
| Pin 58 | VCCIO9 — I/O bank 9 supply voltage |
| Pin 59 | I/O — General purpose user I/O (bank 9) |
| Pin 60 | I/O — General purpose user I/O (bank 9) |
| Pin 61 | I/O — General purpose user I/O (bank 9) |
| Pin 62 | I/O — General purpose user I/O (bank 10) |
| Pin 63 | VCCIO10 — I/O bank 10 supply voltage |
| Pin 64 | I/O — General purpose user I/O (bank 10) |
| Pin 65 | I/O — General purpose user I/O (bank 10) |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — General purpose user I/O (bank 10) |
| Pin 68 | I/O — General purpose user I/O (bank 10) |
| Pin 69 | I/O — General purpose user I/O (bank 11) |
| Pin 70 | VCCIO11 — I/O bank 11 supply voltage |
| Pin 71 | I/O — General purpose user I/O (bank 11) |
| Pin 72 | I/O — General purpose user I/O (bank 11) |
| Pin 73 | I/O — General purpose user I/O (bank 11) |
| Pin 74 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 75 | GND — Ground |
| Pin 76 | I/O — General purpose user I/O (bank 11) |
| Pin 77 | I/O — General purpose user I/O (bank 12) |
| Pin 78 | VCCIO12 — I/O bank 12 supply voltage |
| Pin 79 | I/O — General purpose user I/O (bank 12) |
| Pin 80 | I/O — General purpose user I/O (bank 12) |
| Pin 81 | I/O — General purpose user I/O (bank 12) |
| Pin 82 | I/O — General purpose user I/O (bank 13) |
| Pin 83 | VCCIO13 — I/O bank 13 supply voltage |
| Pin 84 | I/O — General purpose user I/O (bank 13) |
| Pin 85 | I/O — General purpose user I/O (bank 13) |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — General purpose user I/O (bank 13) |
| Pin 88 | I/O — General purpose user I/O (bank 13) |
| Pin 89 | I/O — General purpose user I/O (bank 14) |
| Pin 90 | VCCIO14 — I/O bank 14 supply voltage |
| Pin 91 | I/O — General purpose user I/O (bank 14) |
| Pin 92 | I/O — General purpose user I/O (bank 14) |
| Pin 93 | I/O — General purpose user I/O (bank 14) |
| Pin 94 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 95 | GND — Ground |
| Pin 96 | I/O — General purpose user I/O (bank 14) |
| Pin 97 | I/O — General purpose user I/O (bank 15) |
| Pin 98 | VCCIO15 — I/O bank 15 supply voltage |
| Pin 99 | I/O — General purpose user I/O (bank 15) |
| Pin 100 | I/O — General purpose user I/O (bank 15) |
| Pin 101 | I/O — General purpose user I/O (bank 15) |
| Pin 102 | I/O — General purpose user I/O (bank 16) |
| Pin 103 | VCCIO16 — I/O bank 16 supply voltage |
| Pin 104 | I/O — General purpose user I/O (bank 16) |
| Pin 105 | I/O — General purpose user I/O (bank 16) |
| Pin 106 | GND — Ground |
| Pin 107 | I/O — General purpose user I/O (bank 16) |
| Pin 108 | I/O — General purpose user I/O (bank 16) |
| Pin 109 | I/O — General purpose user I/O (bank 1, reverse side) |
| Pin 110 | VCCIO1 — I/O bank 1 supply voltage (reverse side) |
| Pin 111 | I/O — General purpose user I/O (bank 1) |
| Pin 112 | I/O — General purpose user I/O (bank 1) |
| Pin 113 | I/O — General purpose user I/O (bank 1) |
| Pin 114 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 115 | GND — Ground |
| Pin 116 | I/O — General purpose user I/O (bank 1) |
| Pin 117 | TCK — JTAG test clock |
| Pin 118 | TMS — JTAG test mode select |
| Pin 119 | TDI — JTAG test data in |
| Pin 120 | TDO — JTAG test data out |
| Pin 121 | nSTATUS — Configuration status (active low) |
| Pin 122 | nCONFIG — Configuration start (active low) |
| Pin 123 | CONF_DONE — Configuration done (open drain) |
| Pin 124 | MSEL0 — Configuration mode select 0 |
| Pin 125 | MSEL1 — Configuration mode select 1 |
| Pin 126 | MSEL2 — Configuration mode select 2 |
| Pin 127 | DCLK — Configuration clock input |
| Pin 128 | DATA0 — Configuration data input |
| Pin 129 | VCCA — PLL analog supply (1.2 V) |
| Pin 130 | GNDA — PLL analog ground |
| Pin 131 | VCCPD — Configuration supply (3.3 V) |
| Pin 132 | I/O — General purpose user I/O (bank 2) |
| Pin 133 | I/O — General purpose user I/O (bank 2) |
| Pin 134 | GND — Ground |
| Pin 135 | I/O — General purpose user I/O (bank 2) |
| Pin 136 | I/O — General purpose user I/O (bank 2) |
| Pin 137 | I/O — General purpose user I/O (bank 3) |
| Pin 138 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 139 | I/O — General purpose user I/O (bank 3) |
| Pin 140 | I/O — General purpose user I/O (bank 3) |
| Pin 141 | I/O — General purpose user I/O (bank 3) |
| Pin 142 | VCCINT — Core supply voltage (1.0-1.2 V) |
| Pin 143 | GND — Ground |
| Pin 144 | I/O — General purpose user I/O (bank 3) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL025YE144C8G is suitable for 6 applications: Industrial I/O Expansion and Protocol Bridging, Motor Control and Variable-Frequency Drives, Video Bridging and Display Processing, Low-Power IoT Edge Gateways, Portable Test and Measurement Instrumentation, Automotive Infotainment Auxiliary Controllers.
Industrial I/O Expansion and Protocol Bridging
The 10CL025YE144C8G is well-suited for industrial I/O expansion cards that need to bridge between legacy fieldbus protocols (RS-485, RS-232, Modbus RTU) and modern Ethernet/IP or PROFINET. Its 24,624 logic elements provide ample headroom for soft-core CPUs (such as the Nios II) plus custom protocol state machines, while the 76 user I/O pins accommodate multiple isolated serial channels and parallel GPIO. The C8 speed grade meets typical 12-100 MHz industrial baud requirements with timing margin. Designers should use the E144 exposed pad for thermal relief and follow Intel's industrial temperature layout guidelines.
Recommended
Motor Control and Variable-Frequency Drives
In variable-frequency motor drives, the 10CL025YE144C8G handles field-oriented control (FOC) loops, PWM generation, and current-sampling coordination. The 66 dedicated 18x18 multipliers accelerate the Park/Clarke transforms and PI controllers used in vector control, while the 4 PLLs provide independent clocks for PWM, ADC, and encoder interfaces. With 1.2V core operation and the low-power 60 nm process, the device fits comfortably inside sealed inverter enclosures with no active cooling. The exposed pad on the E144 package is essential for dissipating the ~1-2 W typical power budget.
Recommended
Video Bridging and Display Processing
The 10CL025YE144C8G can be used in video format converters, scalers, and LVDS-to-MIPI bridges for industrial displays and machine vision interfaces. Its M9K memory blocks (608 Kbit total) buffer line-scan or area-scan image data, and the multiplier array supports simple scaling and color-space conversion algorithms. The 76 I/O pins accommodate LVDS pairs and parallel RGB interfaces at moderate resolutions. Designers should use Quartus Prime's Video and Image Processing Suite IP for accelerated development and observe strict length-matched routing for LVDS channels.
Recommended
Low-Power IoT Edge Gateways
For battery- or solar-powered edge gateways aggregating sensor data before forwarding to the cloud, the 10CL025YE144C8G offers a compelling combination of low static power (~70-100 mW idle) and sufficient logic to run a soft-core plus cryptographic accelerators. The C8 speed grade supports typical LoRaWAN, BLE, and sub-GHz radio host-controller duties. With 1.0-1.2V core operation, the device remains within the budget of a small solar-harvested supply. Designers should leverage Quartus' power-aware synthesis and clock-gating to extend battery life further.
Recommended
Portable Test and Measurement Instrumentation
Portable oscilloscopes, data loggers, and bench-top test instruments benefit from the 10CL025YE144C8G's high multiplier count for DSP-based filtering and FFT operations, plus its M9K memory for sample buffering. The exposed-pad E144 package allows the device to fit inside handheld enclosures without active cooling. Designers can implement custom trigger logic, decimating filters, and on-screen display (OSD) generation entirely in fabric. Quartus' DSP Builder toolchain accelerates Simulink-based DSP development for these applications.
Recommended
Automotive Infotainment Auxiliary Controllers
Although not AEC-Q100 qualified itself, the 10CL025YE144C8G is used in non-safety automotive applications such as head-unit auxiliary controllers, dashboard illumination drivers, and HMI expansion. Its 24K logic elements support multiple LIN/CAN soft controllers and LED-matrix drivers simultaneously. The 144-EQFP footprint is a common form factor for behind-dash modules. Designers targeting safety-critical automotive functions should select the AEC-Q100-qualified Cyclone 10 LP -Q variant or move to a different family.
Recommended
Recommended Products Summary
Engineering reference data for 10CL025YE144C8G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL025YE144C6G | 10CL025YE144A7G | 10CL025YE144I7G | 10CL016YE144C8G | 10CL010YE144C8G | 10CL006YE144C8G |
|---|---|---|---|---|---|---|---|
| Package | 144-EQFP (E144, 22x22 mm) | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same | 144-EQFP (E144) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 24,624 | 24,624 | 24,624 | 24,624 | 15,408 | 10,320 | 6,272 |
| Embedded Memory (bit) | 608,256 | 608,256 | 608,256 | 608,256 | 504,000 | 414,000 | 270,000 |
| 18x18 Multipliers | 66 | 66 | 66 | 66 | 56 | 46 | 30 |
| Speed Grade | C8 | C6 (slower) | A7 (faster) | I7 (industrial) | C8 | C8 | C8 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C | 0C to +85C | 0C to +85C |
| Approx. Unit Price (1 pc) | $63.41 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Balanced logic density with low static power (vs Cyclone IV EP4CE25E144)
- C8 speed grade at lower cost than A7 variant (vs 10CL025YE144A7G)
- Commercial temp at minimum cost in the 25K-LE class (vs 10CL025YE144I7G)
- Expandable logic capacity on the same PCB (vs 10CL016YE144C8G)
Design Notes
The 10CL025YE144C8G requires multiple supply rails: VCCINT (1.0-1.2 V core), VCCIOx per bank (1.2-3.3 V), VCCA (1.2 V PLL analog), and VCCPD (3.3 V configuration). Intel recommends a specific power-up sequence (VCCINT before VCCPD before VCCIO) to prevent latch-up; use a supervisor IC such as the ADM1184 to enforce this. Place 100 nF decoupling capacitors within 5 mm of every VCCINT and VCCIO pin, with bulk 10-47 uF tantalum or polymer capacitors on each rail. The exposed pad (EP) must be soldered to a continuous ground plane to minimize thermal resistance.
Estimated: at 25% logic utilization, 50 MHz typical toggle rate, and 1.2 V VCCINT, the 10CL025YE144C8G dissipates approximately 1.0-1.5 W. With the E144 package theta_JA of approximately 28 C/W on a 4-layer JEDEC test board, the junction-to-ambient temperature rise is roughly 28-42 C. For commercial-grade (0C to +85C) operation, this leaves a margin of about 40-55 C above the maximum 85C ambient. In a sealed enclosure with limited airflow, derate by adding thermal vias under the exposed pad and enlarging the top-side copper pour to at least 1 square inch.
The 144-EQFP package has a 0.5 mm pitch and a 22x22 mm body. Route signals on inner layers to break out from the dense perimeter pins; allow at least 4 routing layers for a clean break-out. Differential pairs (LVDS) must be length-matched to within 150 mil; high-speed memory interfaces (DDR3) require strict impedance control of 50 ohm single-ended and 100 ohm differential. Quartus Prime's Pin Planner and the E144 board-level symbol library should be used to validate the schematic before tape-out.
Do not leave the nCONFIG pin floating during normal operation - it must be pulled high to VCCPD through a 10 kohm resistor, or the device will not enter user mode after configuration. Similarly, MSEL[2:0] must be tied to a valid configuration mode (e.g., 000 = AS standard, 001 = AS fast, 010 = PS, 100 = JTAG-only) and not left floating. The nSTATUS and CONF_DONE pins require external 10 kohm pull-ups to VCCPD. Refer to the Cyclone 10 LP Device Family Pin Connection Guidelines for the complete checklist.
Place the 50 MHz or 100 MHz configuration clock source (typically a dedicated oscillator) within 25 mm of the DCLK pin and shield the trace with ground vias. For Active Serial (AS) configuration using an EPCS or EPCQ flash, route the AS_DO, AS_CS, and DCLK traces as a matched-length group with no stubs. Keep JTAG signals (TCK, TMS, TDI, TDO) away from switching power and high-frequency I/O to prevent programming failures.
Compliance Information
RoHS and REACH compliant per Cyclone 10 LP product family datasheet. Not AEC-Q100 qualified - select AEC-Q100 variant for automotive safety-critical applications.
